Method of Making a Microelectronic and/or Optoelectronic Circuitry Sheet

ABSTRACT

A circuitry sheet comprising an electronic device layer stack containing electronic devices, e.g., thin-film transistors, or portions thereof, formed by removing material from both sides of the device layer stack. The circuitry sheet may be made by an electronic/optoelectronic device manufacturing method that includes the steps of forming the device layer stack on a temporary substrate removing material from both sides of the device layer stack, and then attaching a permanent substrate to the device layer stack. The method uses one or more resist layers that may be activated simultaneously and independently to impart distinct circuit pattern images into each of a plurality of image levels within each resist layer, thereby obviating repetitive sequential exposure, registration and alignment steps.

RELATED APPLICATION DATA

This application is a continuation of U.S. patent application Ser. No.11/223,515 filed on Sep. 9, 2005, and titled “Method Of Making AMicroelectronic And/Or Optoelectronic Circuitry Sheet” now U.S. Pat. No.______, that is incorporated herein by reference in its entirety andclaims the benefit of priority of U.S. Provisional Patent ApplicationSer. No. 60/608,328, filed Sep. 10, 2004, and titled “Method ForManufacturing Roll To Roll Electronics,” U.S. Provisional PatentApplication Ser. No. 60/616,530, filed Oct. 7, 2004, and titled“Additional Manufacturing Methods For Roll To Roll Electronics,” andU.S. Provisional Patent Application Ser. No. 60/673,519, filed Apr. 22,2005, titled “Additional Addendum To Method Of Manufacturing Roll ToRoll Electronics,” each of which is also incorporated by referenceherein in its entirety.

FIELD OF THE INVENTION

The present invention generally relates to the field of microelectronicsand optoelectronics. In particular, the present invention is directed toa microelectronic or optoelectronic circuitry sheet and method of makingsame.

BACKGROUND OF THE INVENTION

The electronic display industry, in its continual quest for increasingefficiency, is constantly scaling up the areal, or sheet, size of thesubstrates (typically glass) carrying the pixel matrices of thedisplays. However, the ever-increasing substrate sizes createsignificant manufacturing and engineering challenges relative to theiruse, handling and transportation. Furthermore, the upfront capitalinvestment in infrastructure needed to process these large sheets ofglass for each subsequent generation of fabrication facility hasballooned to upwards of $2 Billion. It is interesting to note that eventhough the underlying substrate sizes have increased, thephotolithography used in fabricating electronic displays is stillperformed using step and scan exposure systems, in which the exposuresize is typically much smaller than the substrate size. Similarly,semiconductors in general are manufactured using multiplephotolithographic steps on ever larger wafers (substrates).

Trends in the display industry, and electronics industry generally,suggest that further display and electronic products will be made onflexible/conformal substrates, and optimally although not necessarily ina roll-to-roll, or reel-to-reel fashion. This transition is seen asinevitable to service the ever-present need and desire to reduce thesize, weight and cost of the products without sacrificing performance. Awide gamut of products from displays, electronics and sensors, to name afew, would benefit from processes that result in the mass production ofruggedized, lightweight, portable, small form factor, less power hungryand lower cost electronic components. In addition, new and novel marketsand opportunities could be addressed and opened up if these componentscould be made flexible and/or conformal.

In order to counter the ever-growing substrate size dilemma and toservice future flexible needs, attempts have been made, and are ongoing,to develop manufacturing processes that would allow for roll-to-roll, orreel-to-reel (also called “web coaters”), technologies to be implementedsuch that flexible substrates, such as polymers/plastic foils and metalfoils, may be substituted for rigid glass substrates. However, attemptsmade have had limited success, primarily due to the complexity ofmanufacturing the electronic devices, such as thin-film transistors(TFTs), of the displays. Typical manufacturing processes for suchdevices include multiple coatings, or layers, deposited at hightemperature, interspaced with multiple photolithography patterningsteps.

It is commonly known that polymers/plastics, if used as substratematerial for electronic devices, severely limit the maximum temperaturethat may be used during the manufacturing of the end product. Inaddition, in order to inhibit undue out-gassing and contamination ofequipment and devices during coating depositions, plastic substratesneed to undergo a complex and time consuming pre-bake thermal cyclingstep. This pre-bake step also serves to expel moisture from the nativepolymer substrate, thereby stabilizing its coefficient of thermalexpansion, which assists in the photolithography patterning andalignment steps.

Metal foils, on the other hand, are more resilient thanpolymers/plastics and tend to be immune from the temperature limitimposed by polymers/plastics. However, to date, TFTs made on metal foilshave exhibited low electronic performance due to contamination effectsand other unknowns attributed to high surface roughness of startingmetal substrates. They are also typically opaque which limits theirusefulness for displays.

Furthermore, the use of flexible substrates has placed heavy demands onengineering new ways and equipment to address: dimensional stability ofsubstrates during lithography; mechanics for handling substratecurvature; registration accuracy; and consistency of placement of TFTsand electrodes. In this connection, flexible polymer/plastic substrateshave had issues with moisture absorption, resistance to chemicals andsolvents.

One of the more significant of the technical challenges to usingflexible substrates that has slowed or stymied attempts at roll-to-rollmanufacturing of electronic devices on either polymers/plastics or metalfoils is the issue with photolithography registration andphotolithography alignment due to the number of coatings and photomasking steps involved in manufacturing traditional TFTs.

FIGS. 1A and 1B illustrate, respectively, a portion of an array 10 ofconventional pixel cells, such as may be found in a number of activematrix backplane type displays, and a cross-section through a portion ofone of the pixel cells. In this example each pixel cell 14 generallycomprises a TFT 18, a storage capacitor 22 and a pixel electrode 24 madeof indium tin oxide (ITO). Referring particularly to FIG. 1B, thevarious layers that make up each cell include a glass substrate layer 28(e.g., a 0.7 mm thick piece of Corning 1737 glass), a gate electrodelayer 32 (made of, e.g., chromium (Cr)), a gate insulator layer 36(e.g., a silicon nitride (SiNx) layer), a pixel electrode layer 40 (madeof, e.g., ITO), a channel layer 44 (e.g., an amorphous silicon (a-Si)layer), an ohmic contact layer 48 (e.g., an n+ a-Si layer), asource/drain metal electrode layer 52 (made of, e.g., Cr) and apassivation layer 56 (e.g., a SiN layer).

Following is a typical conventional set of steps, or recipe, that amanufacturer may use to form pixel cells 14 of FIGS. 1A-B:

-   Step #1: prepare staging area;-   Step #2: clean glass substrate 28;-   Step #3: sputter deposit gate metal layer 32;-   Step #4: clean, coat and cure photoresist (not shown);-   Step #5: align mask 1 (not shown) and expose;-   Step #6: develop resist, etch gate metal, strip photoresist and dry    with air knives;-   Step #7: deposit silicon nitride layer 36, amorphous silicon (or    polysilicon) layer 44 and n+ dopant layer 48;-   Step #8: clean, coat and cure photoresist (not shown);-   Step #9: align mask 2 (not shown) and expose;-   Step #10: develop resist, rinse and dry with air knives;-   Step #11: dry etch a-Si pattern into layers 44 and 48 and strip    photoresist;-   Step #12: ultrasonic clean;-   Step #13: sputter deposit ITO layer 40;-   Step #14: clean, coat and cure photoresist (not shown);-   Step #15: align mask 3 (not shown) and expose;-   Step #16: develop, etch ITO layer 40, strip photoresist and dry with    air knives;-   Step #17: sputter deposit S/D and interconnect metal layer 52;-   Step #18: clean, coat and cure photoresist (not shown);-   Step #19: align mask 4 (not shown) and expose;-   Step #20: develop, etch S/D and interconnect metal layer 48, strip    photoresist and dry with air knives;-   Step#21: dry etch n+ doped layer 48;-   Step #22: deposit passivation layer 56 using plasma-enhanced    chemical vapor deposition;-   Step #23: clean, coat and cure photoresist (not shown);-   Step #24: align mask 5 (not shown) and expose;-   Step #25: develop and rinse photoresist and dry with air knives;-   Step #26: dry etch passivation layer and strip photoresist;-   Step #27: ultrasonic clean;-   Step #28: test and review; and-   Step #29: laser repair shorts.    It is noted that this recipe is for a traditional rigid platform.    Converting this to a roll-to-roll process may also require    intermediary steps of unwinding and rewinding the substrate roll    between steps if the process is not continuous, and some degree of    winding and unwinding is unavoidable in transporting the working    substrate between stations in a continuous process. Note in the    foregoing recipe the number of masks required, each requiring that a    mask must be aligned in order for the corresponding subsequently    patterned layer to be in proper registration with the other layers    so as to create properly functioning devices. These alignment steps    are a hindrance to achieving high device yield and efficient    processing, especially in a roll-to-roll process wherein these    alignment steps must be performed in conjunction with unwinding and    rewinding, which makes the aligning all the more difficult.

Various efforts to date have demonstrated low pixel density TFTs havingmarginal performance on metal/polyimide substrates. However, what isreally needed by the industry as a whole is a methodology that uses alow mask count TFT design and that has roll-to-roll continuousprocessing capability and that utilizes techniques and equipment thatcircumvent issues such as photolithography registration and alignment.The present invention includes such a methodology that essentiallyrenders irrelevant dimensional stability of the substrate due totemperature and allows for the realization of high-resolution displaysand the fabrication of other electronic products.

SUMMARY OF THE INVENTION

One aspect of the present invention is a method defining at least onedefined feature in a substrate, comprising: a) providing a substrate; b)applying a first lower photoresist layer on the substrate; c) applying afirst upper photoresist layer on the first lower photoresist layer so asto form a first photoresist stack; d) exposing the first upperphotoresist layer through a first mask; e) exposing the first lowerphotoresist layer through a second mask and through the first upperphotoresist layer simultaneously with the exposing of the first upperphotoresist layer with the first mask so as to impart a first image ofat least one first structure into the first photoresist stack; f)developing the first upper photoresist layer and the first lowerphotoresist layer so that openings form in each of the first upperphotoresist layer and the first lower photoresist layer to define the atleast one first structure in the first photoresist stack; and g)performing an etch to transfer the at least one first structure formedin the first photoresist stack into the substrate so as to form a firstdefined feature in the substrate.

Another aspect of the present invention is a method of defining at leastone defined feature in a substrate, comprising: a) providing asubstrate; b) applying a first unitary photoresist layer on thesubstrate; c) exposing the first unitary photoresist layer through afirst mask; d) exposing the first unitary photoresist layer through asecond mask simultaneously with the exposing of the first unitaryphotoresist layer with the first mask so as to impart an image of atleast one first structure into the first unitary photoresist layer; e)developing the first unitary photoresist layer to define the at leastone first structure; and f) performing an etch to transfer the at leastone first structure formed in the first unitary photoresist layer intothe substrate so as to form a first defined feature in the substrate.

BRIEF DESCRIPTION OF THE DRAWINGS

For the purpose of illustrating the invention, the drawings show a formof the invention that is presently preferred. However, it should beunderstood that the present invention is not limited to the precisearrangements and instrumentalities shown in the drawings, wherein:

FIGS. 1A and 1B are, respectively, a plan view of a portion of aconventional active matrix backplane and an enlarged partialcross-sectional view of a pixel cell of the backplane as taken alongline 1B-1B of FIG. 1A;

FIGS. 2A-2B is a flow diagram illustrating an electronic devicemanufacturing (EDM) method of the present invention;

FIGS. 3A-3O are partial cross-sectional views of layered structuresformed during various steps of the EDM method of FIGS. 2A-B;

FIGS. 4A-4C are cross-sectional views, respectively, a binary mask, agrayscale mask and a color mask suitable for use with EDM method ofFIGS. 2A-B;

FIG. 5 is graph illustrating the absorption of a resist material beforeand after exposure in the context of a wavelength X;

FIGS. 6A-6D are partial cross-sectional views of a resist layerillustrating the formation of three images on three distinct imagelayers within the resist layer;

FIG. 7 is a high-level schematic of a dual wavelength maskless directlaser writing lithography system of the present invention that may beused with EDM method of FIGS. 2A-B;

FIGS. 8A-8V contain partial cross-sectional views of layered structuresformed during various steps of the particular recipe of Example 1 forthe EDM method of FIGS. 2A-B; FIGS. 8M and 8Q2 each also contain a planview of a mask pattern applicable to the corresponding respective stepof the recipe, and FIG. 8Q 3 shows an overlay of the mask patterns ofFIGS. 8M and 8Q2;

FIGS. 9A-9V contain partial cross-sectional views of layered structuresformed during various steps of the particular recipe of Example 2 forthe EDM method of FIGS. 2A-B; FIGS. 9M and 9P1 each also contain a planview of a mask pattern applicable to the corresponding respective stepof the recipe, and FIG. 9P 2 shows and overlay of the mask patterns ofFIGS. 9M and 9P1;

FIGS. 10A-10U contain partial cross-sectional views of layeredstructures formed during various steps of the particular recipe ofExample 3 for the EDM method of FIGS. 2A-B; FIGS. 10M and 10R1 each alsocontain a plan view of a mask pattern applicable to the correspondingrespective step of the recipe, and FIG. 10R 2 shows an overlay of themask patterns of FIGS. 10M and 10R1;

FIGS. 11A-11V contain partial cross-sectional views of layeredstructures formed during various steps of the particular recipe ofExample 4 for the EDM method of FIGS. 2A-B; FIGS. 11N and 11S1 each alsocontain a plan view of a mask pattern applicable to the correspondingrespective step of the recipe, and FIG. 11S 2 shows an overlay of themask patterns of FIGS. 11N and 11S1;

FIG. 12 is a plan view of an overlay of the mask patterns of FIGS. 8Mand 8Q2;

FIGS. 13A-13AB contain partial cross-sectional views of layeredstructures formed during various steps of the particular recipe ofExample 5 for the EDM method of FIGS. 2A-B; FIGS. 13N, 13Q and 13W1 eachalso contain a plan view of a mask pattern applicable to thecorresponding respective step of the recipe, and FIG. 13W 2 shows anoverlay of the mask patterns of FIGS. 13N, 13Q and 13W1;

FIGS. 14A-14AD contain partial cross-sectional views of layeredstructures formed during various steps of the particular recipe ofExample 6 for the EDM method of FIGS. 2A-B; FIGS. 14P, 14T, 14Z and14AB1 each also contain a plan view of a mask pattern applicable to thecorresponding respective step of the recipe, and FIG. 14AB2 shows anoverlay of the mask patterns of FIGS. 14P, 14T, 14Z and 14AB1;

FIGS. 15A-15AH contain partial cross-sectional views of layeredstructures formed during various steps of the particular recipe ofExample 13 for the EDM method of FIGS. 2A-B; FIGS. 15Q, 15U, 15AA and15AE each also contain a plan view of a mask pattern applicable to thecorresponding respective step of the recipe; and

FIG. 16 is a high-level schematic of a roll-to-roll manufacturing systemof the present invention.

DETAILED DESCRIPTION

FIGS. 2A-B illustrate in accordance with the present invention anelectronic/optoelectronic device manufacturing (EDM) method, which isgenerally indicated by the numeral 200. EDM method 200 includes a numberof unique steps and series of steps for efficiently producing any of awide variety of electronic devices and electrical interconnectingstructures. Examples of electronic devices that can be made using an EDMmethod of the present invention, such as EDM method 200, include, amongothers: transistors, e.g., thin-film transistors (TFTs) and thick-filmtransistors; diodes, e.g., metal-insulator-metal diodes, laser diodes,ring oscillators, etc.; interconnect metallization layers; passiveelements such as capacitors, resistors, and inductors; and completesensors and transducers, among others. Regarding TFTs in particular,they may be made of any of a variety of materials, e.g., CdSe, amorphoussilicon, high temperature poly silicon, low temperature poly silicon,ultra-low temperature poly silicon and polymers, among others. TFTs madein accordance with the present invention may be of either of the PMOS orNMOS types. In addition, they may have planar or staggered structuresand may be of the bottom- or top-gate variety, etc. As will be apparentfrom reading this entire disclosure, there is virtually an infinitevariety of device architectures in current use, each tailored foroptimum devices performance, that can be readily be translated to an EDMmethod of the present invention, such as EDM method 200. Examples ofelectrical interconnecting structures include wires, studs, electrodesand pixel conducting elements, e.g., pixel electrodes, among other.Those skilled in the art will readily appreciate that the foregoinglists of devices and electrical interconnecting structures are merelyrepresentative and by no means exhaustive.

In general, an EDM method of the present invention may be used to makean electronic and/or optoelectronic circuitry sheet, such as circuitrysheet 322 of FIG. 30, that contains, or contains precursors to, aplurality of one or more types of electronic device arranged andinterconnected with one another so as to form a functional component ofan electronic product. For example, a circuitry sheet of the presentinvention may be, or may be a precursor to, an active matrix backplanefor a display device, a sensor array for a sensing device, an antennaelement of a phased array antenna, radio frequency identification (RFID)circuitry for an RFID tag or a microprocessor for an electronic productcontaining one or more microprocessors, among many others. Those skilledin the art will readily appreciate that a circuitry sheet of the presentinvention is in no way limited to any particular function or set offunctions. In addition, it should be appreciated that the word “sheet”as used herein and in the claims appended hereto in connection with theterm “circuitry sheet” and similar terms does not imply any particularfacial area or thickness or that the structure described thereby isflexible or rigid to one extent or another. Rather, the use of “sheet”in this context is used to indicate that the structure has at least onelineal facial dimension that is greater than the maximum thickness ofthe structure.

At a very high level, novel features of an EDM method of the presentinvention include, but are not limited to: (1) using a temporarysubstrate to deposit a stack device electronic device layers and thesubsequent transfer process onto another permanent substrate; (2)dual-sided processing of a device layer stack; (3) simultaneouslyexposing either one or both top and bottom resist layers of the devicelayer stack with different patterns; (4) using resist layers eachcontaining a plurality of imaging levels; (5) using more than onewavelength (or other resist actuation impulse/stimuli) per surface ofthe device layer stack to expose of the resist layer(s) at the sametime; and (6) allowing for unique recipes that decouple the electronicdevice layers from multiple lithography alignment steps.

In addition, as will become apparent from the reading this entiredisclosure, an EDM method of the present invention may be used to createa variety of devices having novel structures that result from the orderin which the steps of the EDM method are performed. For example, FIG.8V, described in detail below, illustrates a unique pixel cell madeusing an EDM method of the present invention. In addition, it will alsobecome apparent from reading the entire disclosure that an EDM method ofthe present invention is readily, though not exclusively, suited toimplementation in a roll-to-roll manufacturing system, such asroll-to-roll system 1600 illustrated in FIG. 16 and described below inmore detail.

In sharp contrast to prior art, an EDM method of the present inventionreveals a methodology that significantly reduces the number ofmanufacturing steps needed to create functioning electronic devices andcircumvents a number of the shortcomings of the prior art. In addition,an EDM method of the present invention allows for adapting and adoptingthe best-of-breed current and evolving manufacturing techniques,technological base and capital investments, and tailors themanufacturing process parameters to suit device performance rather thansubstrate selection. An EDM of the present invention thus decouples thechoice of final substrate from the device performance needed.

Prior to describing particular aspects, results and implementations ofthe present invention, attention will first be directed to presenting ahigh-level description of EDM method 200, which is a representativemethod of the present invention. Following the high-level description,various aspects of the various step EDM method 200 will be described insome detail, followed still by some examples of recipes for making pixelcells using an EDM method of the present invention and some disclosuredirected to other implementations of the present invention.

EXEMPLARY METHODOLOGY OF THE PRESENT INVENTION

Referring again to FIGS. 2A-B, and also FIGS. 3A-3O (in this section,the alphabetic step identifier, e.g., “B” in “step B,” corresponds tothe relevant figure of FIGS. 3A-3O), EDM method 200 may begin at step Ain which an appropriate temporary substrate 300 may be selected for adesired application. In general, temporary substrate 300 provides aplatform for forming a stack 304 (FIG. 3E) of electronic device layers308 (FIG. 3E), i.e., the layers that make up some or all of theelectronic devices made using EDM method 200. Temporary substrate 200should be selected based on the properties necessary to permit theproper formation of device layer stack 304. It is noted that temporarysubstrate 300 may be either rigid or flexible so as to accommodateroll-to-roll processing. A rigid embodiment of temporary substrate wouldstill allow for sheet-to-sheet production. At a certain point within EDMmethod 200, temporary substrate 300 will be removed to allow certainsteps to be performed. Temporary substrate is described in more detailbelow in the section titled “Temporary Substrate”.

It is also note that the term “temporary” as used herein and in theappended claims does not necessarily mean that temporary substrate 300will eventually be removed or will not serve a useful purpose afterdevice layer stack 304 has been formed. On the contrary, in someapplications temporary substrate 300 will indeed remain part of thefinished structure and in other applications the temporary substratewill not only remain part of the finished structure, but will also servea particular function of the finished structure. Consequently, the term“temporary” as used in this disclosure indicates that substrate 300 isused early in EDM method 200 for forming device layer stack 304, butlater in the method another substrate is affixed to the device layerstack.

If temporary substrate 300 is flexible and such flexibility is notdesired in at least some of the subsequent steps of EDM method 200, at aconditional step B a backing substrate, or “stiffener” 312 may be addedto the temporary substrate to provide mechanical support for thesubstrate during some of the subsequent processing steps. Stiffener 312is described in more detail below in the section titled “Stiffener”.

Depending on the nature of temporary substrate 300 chosen in step A, aconditional step C may be necessary or desirable to apply a planarizinglayer 316 to the temporary substrate. For example, if surface 320 oftemporary substrate is too rough or otherwise is not of a quality neededfor subsequent steps of EDM method, it may be desirable to provideplanarizing layer 312. Planarizing layer is described in more detailbelow in the section titled “Planarizing Layer”.

Since temporary substrate 300 and stiffener 312, if present, will inmost cases be removed from stack 304 (FIG. 3E), at conditional step D itmay be necessary or desirable to provide one or more suitable releaselayers 324 that will aid in detaching the temporary substrate from thestack. Various materials suitable for use in forming release layer 324and other disclosure pertaining to the release layer are described belowin the section titled “Release Layer(s)”.

At step E, the various electrical device layers 308 may be deposited soas to form device layer stack 304. If planarizing layer 316 wasimplemented at step C, the first electrical device layer 308 may bedeposited onto the planarizing layer. If one or more release layers 324was provided at step D, the first electrical device layer may bedeposited on the free surface of such layers. Otherwise, the firstelectrical device layer 308 will be formed on surface 320 of temporarysubstrate 300, unless one or more other layers, e.g., a passivationlayer (not shown) had been previously deposited onto the temporarysubstrate. Again, as mentioned above, electrical device layers 308 arelayers that make up all or part of each electronic device that is partof the finished circuitry sheet 322 (FIG. 30). It is stressed that notall layers that make up an electronic device in a given recipe mayalways be deposited in step E. However, certain benefits of the presentinvention result from depositing as many as practicable of theelectronic device layers that have the most stringent or criticaldeposit photolithography patterning and alignment requirement. If for agiven recipe fewer than all of the ultimate device layers can bedeposited as device layers 308 of device layer stack 304, the remaininglayers may be deposited later in the process. It is noted that devicelayer stack 304 may be formed in a single coating that has beenappropriately doped so as to form multiple active layers within thecoating. In this case, the active layers correspond respectively to theelectronic device layers 308 shown in FIG. 3E. Electronic device layers308 are discussed in more detail below in the section titled “DeviceLayer Stack”.

After all electronic device layers 308 have been deposited, at step F aresist layer 328 may be deposited onto the outer face 332 ofas-yet-unpattemed device layer stack 304. For some applications a singleresist coating that functions as a single imaging level is sufficient.However, for some applications it may be desirable to have two or moreimaging levels within resist layer 328 that are distinct from eachother. As described in more detail below, multiples imaging levels maybe provide using a single resist coating or several resist coatings. Inyet other cases, it may be desirable to provide multiple resist coatingsthat function so as to provide a single imaging level. Resist layer 328and single and multiple resist coatings are addressed in more detailbelow in the sections titled “Resist Layers” and “LithographyTechniques”.

In some cases it may be desirable to protect resist layer 328 formed instep F from damage that could occur during subsequent processing steps.If so, in conditional step G a protective layer 336 may be applied toresist layer 328. Depending upon the nature of subsequent processingsteps and the robustness of resist layer 328, protective layer 336 neednot be provided. The below section titled “Protective Layer” describessuitable materials for and methods of providing protective layer 336.

Following step F or G, depending on whether or not protective layer 336is provided, at conditional steps H1-H5 some or all of temporarysubstrate 300, temporary stiffener 312 and/or release layer 324 may beremoved from device layer stack 304 in order to process the second sideof the device layer stack. In general, the layers removed and the extentof their removal will depend, obviously, on their presence and on theeffect of their remaining in place during subsequent processing. Inmany, but not all, cases at least some material will be removed from thestructure resulting after step F or G. For example, if temporarysubstrate 300 is thin, e.g., <1000 microns, and stiffener 312 is notused, then the temporary substrate may be left intact if it does notinterfere with subsequent processing. If temporary substrate 300 is thinand stiffener 312 is present, at step H1 only the stiffener may beremoved leaving the temporary substrate intact, if the temporarysubstrate does not interfere with subsequent processing.

However, if temporary substrate 300 must be at least partially removedto facilitate further processing, at step H2, temporary substrate 300,and stiffener 312 if it is present, may be completely removed.Alternatively, at step H3, temporary substrate 300 (and all of stiffener312) may be partially removed. As another alternative, at step H4 all ofrelease layer(s) 324, if present, may be removed in addition to theremoval of temporary substrate 300 and/or stiffener 312. As yet anotheralternative, at step H5 only part of release layer(s) 324, if present,may be removed in addition to the removal of temporary substrate 300and/or stiffener 312. The removal of release layer(s) 324, temporarysubstrate 300 and/or stiffener 312 is discussed in more detail below inthe section titled, “Techniques For Detaching Device Layer Stack FromTemporary Substrate”.

Next, at step I a resist layer 340 may be formed on the surface thatremains on the side opposite resist layer 328 after the performance ornonperformance of any one of steps H1-H5. Resist layers 340 may besimilar to resist layer 328 discussed above.

After resist layer 340 has been formed in step I, at conditional step Ja protective layer 344 may be provided to protect the resist layer ifsuch protection is desired. If provided, protective layer 344 may besimilar to protective layer 336 discussed above.

After resist layer 340 has been formed, or if protective layer 344 hasbeen provided to resist layer 340, after protective layer 344 has beenformed, at step K resist layers 328, 340 may be exposed in anyappropriate manner, e.g., using electromagnetic energy (such as light346), thermal energy or sonic energy, among others, that exposes, oractivates, the intended images layers contained within the resist layerswith the corresponding respective prescribed patterns (not shown). Theexposure of resist layers 328, 340 may be performed simultaneously withone another or at different times. The exposures may be carried outusing either conventional masking technology or maskless techniques.Techniques for exposing resist layers 328, 340 are discussed in detailbelow in the sections title “Exposure Mechanism For Chosen ResistMaterial” and “Lithography Techniques”.

At step L, after resist layers 328, 340 have been exposed in step K,protective layers 336, 344, if present, and predetermined portions ofones of electronic device layer 308 may be removed, e.g., etched orablated, as required by the particular recipe for the specificelectronic device sheet being made. A variety of removal techniquessuitable for use in step L are described in detail in the section titled“Etching Device Layer Stack”.

After removing all of the material desired from device layer stack 304and other layers, the remaining structure may be attached to a desiredpermanent substrate 348 in step M. As discussed below in the sectiontitled “Permanent Substrate”, permanent substrate 348 may be made of anymaterial suitable for the particular application. In some applications,it may be desired that permanent substrate 348 be opaque. In otherapplications, it may be desired that permanent substrate 348 betransparent or translucent. EDM method 200 can accommodate any of thesesubstrates. The below section titled “Laminating Permanent Substrate ToPatterned Device Layer Stack” described techniques that may be used toattached permanent substrate 348 to the structure containing devicelayer stack 304.

At conditional step N, any remaining permanent layers 352 may bedeposited onto the side of circuitry sheet 322 opposite permanentsubstrate 348 and patterned as needed, if at all. Such additionallayer(s) 352 may include device layers not part of device layer stack304, one or more passivation layers 356 and conductor layers, amongothers. Like other layers, permanent layer(s) may be transparent,translucent or opaque to suit a particular application. For additionalinformation regarding various types of permanent layers 352 referencemay be made to the below section titled “Electronic Device Layer Stack”relative to device layers and the below section titled “PassivationMaterial” relative to passivation layers.

At step O, permanent layers 352 may be patterned as necessary and themanufacturing steps may concluded. Finished circuitry sheet 322 may beinspected, further processed, incorporated into a product, package orcomponent of a product, etc. as needed.

DETAILED DESCRIPTION OF ASPECTS OF EXEMPLARY METHODOLOGY

In order to give the reader a better sense of the broad scope of thepresent invention, certain steps and other aspects of the exemplarymethodology of the present invention described above are discussed belowin greater detail.

Temporary Substrate

As mentioned above, temporary substrate 300 serves as a platform for theformation of device layer stack. Temporary substrate 300 may, but neednot, be removed in subsequent processing steps. There is a vast varietyof materials of which temporary substrate 300 may be made in connectionwith the present invention. As also mentioned, temporary substrate 300can be either flexible or rigid. Flexible substrates suitable for use astemporary substrate 300 include, but are not limited to, polymers,metals, paper, fabric, glass and combinations thereof. Rigid substratesfor use as temporary substrate 300 include, but are not limited to,ceramics, metals, glass, semiconductors, and combinations thereof.Temporary substrate may be transparent, opaque or translucent.

Depending on the application under consideration, the material chosenfor temporary substrate 300 may be a conductor, an insulator or asemiconductor and further may be inorganic or organic or a combinationthereof. Suitable conductor materials may include metals such asaluminum, copper, steel, carbon steel, magnesium, stainless steel,titanium, super alloys, lead, nickel, brass, gold, silver, platinum,rhodium, incoloy, inconel, iron, molybdenum, monel, nichrome, chromium,tantalum, tin, tungsten, zinc, solder (Sb/Tn), invar, kovar, etc. Theirrespective alloys may also be used. Furthermore, the metals may benon-tempered or tempered. Suitable conductor materials may also includegraphite sheets, and conductive carbon nanotube sheets, films and foils.

Suitable insulator materials may be natural or synthetic and may havechemical compositions containing oxides, sulphides, selenides,tellurides, fluorides, chlorides, bromides, iodides, borides, nitrides,carbides, phosphides, arsenides, silicides or any combination thereof.Suitable insulator materials may also include glass, glass with polymersheets, ceramic mats, ceramic paper, or ceramic fibers. The insulatormaterial may be selected from metal oxides, metal nitrides, metalcarbides, metal oxynitrides, metal oxyborides, or combinations thereof.The metallic component of these materials may be selected from aluminum,titanium, indium, tin, tantalum, zirconium, niobium, hafnium, yttrium,nickel, tungsten, chromium, zinc, alloys thereof or combinationsthereof. The metal oxide or sub-oxide selected may be from siliconoxide, aluminum oxide, titanium oxide, indium oxide, tin oxide, indiumtin oxide, tantalum oxide, zirconium oxide, niobium oxide, hafniumoxide, yttrium oxide, nickel oxide, tungsten oxide, chromium oxide, zincoxide, or combinations thereof. The metal nitride selected may be fromaluminum nitride, silicon nitride, boron nitride, germanium nitride,chromium nitride, nickel nitride, gallium nitride, or combinationsthereof. The metal carbide selected may be from boron carbide, tungstencarbide, silicon carbide, or combinations thereof. The metal oxynitrideselected may be from aluminum oxynitride, silicon oxynitride, boronoxynitride, or combinations thereof. The metal oxyboride selected fromzirconium oxyboride, titanium oxyboride, or combinations thereof.

Semiconductors materials may be silicon, germanium, AlGaAs, GaAs, GaP,InP,ZnO, ZnS, ZnSe, GaN, etc. Suitable opaque cermets may be selectedfrom zirconium nitride, titanium nitride, haffiium nitride, tantalumnitride, niobium nitride, tungsten disilicide, titanium diboride,zirconium diboride, or combinations thereof.

Organic materials may include organic polymers, inorganic polymers,organometallic polymers, hybrid organic/inorganic polymer systems. Theorganic polymer may be selected from urethanes, polyamides, polyimides,polybutylenes, isobutylene isoprene, polyolefins, epoxies, parylene,benzocyclobutadiene, polynorbomenes, polyarylethers, polycarbonate,alkyds, polyaniline, ethylene vinyl acetate, and ethylene acrylic acid,(meth)acrylates, etc. Examples of organic polymers, include, forexample, polyethlyene terephthalate (PET), polyethylene naphthalate(PEN), or high temperature polymers such as polyether sulfone (PES),polyimides, or TransphanTM polymer (a high Tg cyclic olefin polymeravailable from Lofo High Tech Film, GMBH of Weil am Rhein, Germany).Other examples include E-CTFE, E-TFE, PTFE, FEP, and HDPE, andpolyimides such as KAPTON®, KAPTON® HN, KAPTON® FN, KAPTON® VN, KAPTON®CR, KAPTON® CB, KAPTON® E polyimides (KAPTON is a registered trademarkof E.I. DuPont de Nemours and Company, Wilmington, Del.), APICAL®polyimide (APICAL is a registered trademark of Kanegafuchi Kagaku KogyoKabushiki Kaisha Corp., Osaka, Japan), and UPILEX® polyimide (UPILEX isa registered trademark of Ube Industries, Ltd., Yamagichi-ken, Japan).

Suitable synthetic organic resins include both thermoplastic resins andthermosetting resins, such as polyolefins, e.g. polyethylene,polypropylene, ethylene-propylene copolymers, and ethylene-vinyl acetatecopolymers (EVAs); cyclic polyolefins; modified polyolefins; polyvinylchloride; polyvinylidene chloride; polystyrene; polyamides;polyamide-imides; polycarbonates; poly-(4-methylpentene-1); ionomers;acrylic resins; polymethyl methacrylate (PMMA);acrylonitrile-butadiene-styrene copolymers (ABS resins);acrylonitrile-styrene copolymers (AS resins); butadiene-styrenecopolymers; polyoxymethylene; polyvinyl alcohol (PVA); ethylene-vinylalcohol copolymers (EVOHs); polyesters, e.g. polyethylene terephthalate(PET), polybutylene terephthalate (PBT), and polycyclohexaneterephthalate (PCT); polyethers; polyether-ketones (PEKs);polyether-ether-ketone (PEEKs); polyether-imides; polyacetals (POMs);polyphenylene oxides; modified polyphenylene oxides; polysulfones;polyphenylene sulfide (PPS); polyether sulfones (PESs); polyarylates;aromatic polyesters (liquid crystal polymers); polytetrafluoroethylene;polyvinylidene fluoride; other fluorine resins; thermoplasticelastomers, e.g. styrene-, polyolefin-, polyvinyl chloride-,polyurethane-, polyester-, polyamide-, polybutadiene-,trans-polyisoprene-, fluorine rubber-, and chlorinatedpolyethylene-type; epoxy resins; phenol resins; urea resins; melamineresins; unsaturated polyesters; silicone resins; and polyurethanes; andcopolymers, blends, and polymer alloys essentially consisting of thesesynthetic resins. One or more of these synthetic resins may be used, forexample, as a composite consisting of at least two layers.

The inorganic polymer may be selected from silicones, polyphosphazenes,polysilazane, polycarbosilane, polycarborane, carborane siloxanes,polysilanes, phosphonitirles, sulfur nitride polmers and siloxanes. Theorganometallic polymer may be selected from organometallic polymers ofmain group metals, transition metals, and lanthanide/actinide metals,e.g., polymetallocenylenes such as polyferrocene and polyruthenocene.Hybrid organic/inorganic polymer system may be selected from organicallymodified silicates, preceramic polymers, polyimide-silica hybrids,(meth)acrylate-silica hybrids, polydimethylsiloxane-silica hybrids andceramers.

New and emerging organic technologies allows for self assembledcrystalline organic layers. These may also be used as a temporarysubstrate platform.

It may be advantageous, though not necessary, to have the thinnesttemporary substrate 300 for a given material choice. The thickness oftemporary substrate 300 may range from a few microns to several hundredmicrons depending on the choice of material and flexibility desiredduring manufacturing. In some cases, like ceramic mats and foils, thethickness could extend into millimeters. There are fundamentally nolimits on thickness. While certain representative embodiments have beenshown for purposes of illustrating the wide variety of materialssuitable for temporary substrate 300, it will be apparent to thoseskilled in the art that materials not disclosed herein may beincorporated without departing from the scope of the invention.

Stiffener

As mentioned above, stiffener 312 might be used, if desired, foradditional mechanical support of temporary substrate 300. Stiffener 312may be made of any of the materials outlined above for temporarysubstrates 300 and may be made of a material different from or identicalto the material of the temporary substrate. As will be apparent to thoseskilled in the art, there are many ways to attached stiffener 312 totemporary substrate 300 using conventional substrate-to-substrateattaching techniques. Such techniques include chemical bonding usingepoxies, adhesive, room-temperature vulcanization, silicones, urethanes,and ceramics, among others. The bonding agent may be cured/activatedusing, e.g., plasma, visible light, ultraviolet light, temperature,pressure, anaerobic environment, etc. Bonding may also be initiated bysurface treatments using chemicals, activated plasma treatments, vacuumprocesses, etc. Bonding processes may also include microwave bonding,anodic bonding, fusion bonding, adhesive, eutectic, resist, solder,thermo-compression and/or low temperature glasses. Attaching may also bedone using rivets, welds, studs, sprokets, clips, etc.

While certain representative embodiments have been shown and describedfor purposes of illustrating a point, it will be apparent to thoseskilled in the art that bonding methods not disclosed herein may be usedwithout departing from the scope of the invention.

Planarizing Layer

As discussed above, temporary substrate 300 chosen for a particularapplication might or might not have satisfactory surface quality. If thesurface quality is unsatisfactory, planarizing layer 316 may bedeposited onto the surface of such a substrate to smooth over (orplanarize) any unevenness due to surface roughness. Additionally,planarizing layer may also serve, among other things, as a thermalbarrier, chemical barrier, stress relief layer and/or passivation layerand may possibly be also used enhance bond strength of subsequent layersto temporary substrate 300.

Planarizing layer 316 may be made of any suitable material, such as spinon glass (SOG), reflow glass compositions such as low temperature oxide(LTO), phosphosilicate glass (PSG), boronphosphosilicate glass (BPSG),polyimides, Quasi-inorganic SOGs Siloxanes (methyl-, ethyl-, phenyl-,butyl-, doped, undoped), purely-inorganic SOGs, silicates (doped orundoped), and dopant-organic compounds, acrylics, epoxies, vinyl-basedchemistries, silicon or metal containing organometallics,butylcyclobuten, various polyimides, radiation-cured monomers andpolymers, UV cured polymers and UV cured monomers, among others.

It is also noted that low-temperature fluxes, solders, eutecticcompositions, metals, metal alloys may be induced to flow under theinfluence of heat or pressure, or both, and therefore be suitable insome applications for planarizing layer 316. For example, in a techniquecalled “contact planarization,” in a first step a malleable coatingwould be applied onto “temporary substrate.” In a second step, thecoated substrate would be pressed against an optically flat surface or,alternatively, rolled under very high precision polished rollers inorder to planarize the coating layer into planarizing layer 316.Planarizing layer 316 may then simultaneously (or posthumously) be curedby heat, pressure, time, UV or visible radiation among other things.

Planarizing layer 316 may be deposited by evaporation techniques such asphysical vapor deposition (PVD), chemical vapor deposition (CVD),atmospheric-pressure CVD (APCVD), PECVD, sputtering, low-pressure CVD(LPCVD), ion plating, flame hydrolysis, etc. Alternatively, planarizinglayer 316 may be applied by other methods such as spin coating;spraying; rolling; plating, such as electroplating, dip-plating, andelectroless-plating; coating, such as a Langmuir-Blodgett process;printing, such as ink jet or powder jet; screening; gravure; bladespreading, etc.

It is noted that there are fundamentally no limits on thickness ofplanarizing layer. It may be as thin as a few nanometers to several tensof microns thick. Alternatively, it is noted that more traditionaltechniques for reducing surface roughness of substrates may be used toplanarize temporary substrate 300. These techniques include, but are notlimited to, electro-polishing, electroless polishing,chemical-mechanical polishing, mechanical grinding and polishing, ionetching and ion polishing, among others.

While certain representative embodiments have been shown for purposes ofillustrating the wide variety of materials that can be used, it will beapparent to those skilled in the art that materials not disclosed hereinmay be used without departing from the scope of the invention.

Release Layer

As discussed above, in some applications it might be desirable toprovide sacrificial release layer 324 formed on planarizing layer 316(or planarized surface 320 of temporary substrate 300) prior todepositing device layer stack 304. Release layer 324 could then serve asa releasing, or exfoliating, layer for separating temporary substrate300 from device layer stack 304 during subsequent processing. Dependingon the particular application, release layer 324 can serve any one ormore of a number of functions. For example, if temporary substrate 300selected were expensive, it may be desirable to reutilize it many times.In this case, release layer 324 would allow this functionality, whichcould provide significant cost savings. Without release layer 324, theonly choice for detaching temporary substrate 300 might be physically orchemically removing it, respectively, by grinding or etching.

In addition, it is widely known that photolithographic resolution isdependent on depth of focus. If temporary substrate 300 were very thick(e.g., because it cannot be made any thinner, for handling issues, orother reason) then high-resolution lithography might not be possible.However, providing release layer 324 would alleviate this issue. Oncedevice layer stack 304 is released from temporary substrate 300, a thinlayer photoresist and high resolution photolithography can be utilized.

Examples of materials suitable for release layer 324 include, but arenot limited to, solvent etched metals such as inconel, gold, copper,NiFe, nickel, platinum, chrome, silver, etc., and their alloys;hygroscopic inorganic salts such as sodium chloride, barium fluoride,calcium oxide, magnesium fluoride, copper sulphate, sodium carbonate,zinc sulphide, lanthanum bromide, etc.; other inorganics like silicon,polysilicon, amorphous silicon layer with entrapped hydrogen gas, nanostructured films, nano colloids, nanofilaments, nanowires, nanoclusters,channel-like voids which are micro-scale voids, nano-scale voids, highsurface to volume column-void network and films, etc.; organics likephotoresist, polyimide, CVD plastic materials, self assembled monolayers(SAM), etc.

Release layer 324 may be formed using a number of different methods,including evaporation techniques such as PVD, CVD, APCVD, PECVD,sputter, LPCVD, ion plating, flame hydrolysis, etc.; spin coating;spraying; rolling; plating, such as electro-plating, dip-plating, andelectroless-plating; coating, such as a Langmuir-Blodgett process;printing, such as ink jet or powder jet; screening; gravure; bladespreading, etc. It is noted that release layer 324 may consist of one ormore release coatings.

There are fundamentally no limits on the thickness of release layer 324.For example, each may be as thin as a few nanometers to several tens ofmicrons thick.

While certain representative embodiments have been shown for purposes ofillustrating the wide variety of materials that can be used, it will beapparent to those skilled in the art that materials not disclosed hereinmay be used without departing from the scope of the invention.

Electronic Device Layer Stack

A typical microelectronic device comprises a number of layers ofcoatings composed of metals, dielectrics and/or semiconductor materials.Some or all of these coating layers may be contained in electronicdevice layer stack 304 as electronic device layers 308. Depending on thenature of the electronic devices formed using an EDM method of thepresent invention, such as EDM method of FIG. 2, device layers 308 maybe organic or inorganic in composition.

If a particular device layer 308 is a metal layer, the coating used toform that layer may be a metallic substance such as, but not limited to,Al, Cu, Mo, Cr, Ta, W, Ni, Ti, Si, Ti—Si, Al—Si, Al—Cu, Ti—Al, andsilicides, among others. Additionally, alloys of metals may also beused. If another device layer 308 is a dielectric layer, the coating forthis layer may include dielectric materials from a group comprisingoxides, nitrides, carbides, and organics, but not limited to thefollowing. For example, the material may be selected from metal oxides,metal nitrides, metal carbides, metal oxynitrides, metal oxyborides, orcombinations thereof. The metallic component of these materials may beselected from aluminum, titanium, tantalum, zirconium, niobium, silicon,hafnium, yttrium, nickel, tungsten, alloys thereof, or combinationsthereof.

If a metal oxide or sub-oxide is selected, it may be selected from amonga group comprising silicon oxide, silicon dioxide, aluminum oxide,titanium dioxide, tantalum pentoxide, zirconium oxide, niobium oxide,haffiium oxide, yttrium oxide, nickel oxide, tungsten oxide orcombinations thereof, among others. If a metal nitride is selected, itmay be selected from among a group comprising aluminum nitride, siliconnitride, boron nitride, germanium nitride, chromium nitride, nickelnitride, gallium nitride, or combinations thereof, among others. If ametal carbide is selected, it may be selected from among a groupcomprising boron carbide, tungsten carbide, silicon carbide, orcombinations thereof, among others. A metal oxynitride may be selectedfrom among a group comprising aluminum oxynitride, silicon oxynitride,boron oxynitride, or combinations thereof, among others. A metaloxyboride may be selected from among a group comprising zirconiumoxyboride, titanium oxyboride, or combinations thereof, among others. Inaddition, low K dielectrics, and organic dielectric materials,polyimides may be substituted as needed for a particular device layer308. The dielectric material may also have other functions such aspassivation, providing a field oxide, stress relieving, providing athermal barrier, providing a chemical barrier and/or enhancing bondstrength to a polymer substrate, among others.

If a particular device layer 308 is a semiconductor layer, the coatingsmay use semiconductor materials from the group consisting of thefollowing, but not limited to: silicon, Ge, SiGe, GaAs, InGaAs, InP,AlGaAs, GaP, InGaP, CdSe, CdS, CdTe, ZnS, ZnSe, ZnO, amorphous silicon,hydrogenated amorphous silicon, polycrystalline silicon,micro-crystalline silicon, nano crystalline silicon, silicon nanowires,monocrystalline silicon, quantum dots, nanodots, SWNT (carbonnanotubes), nanoshells, nanocrystals, quantum islands and quantum wires,among others. Since a method of the present invention has wideapplication, the semiconductor materials may also be organic in nature.In addition, the semiconductor materials may be doped or undoped.Typical dopant gases such as PF₅, BF₃, B₂ H₆, and AsF₅, among others,may be utilized.

Furthermore, if the as-deposited semiconductor layer is amorphous orsmall grained, it may be further re-crystallized to yield higher carriermobility and associated performance benefits using known and emergingre-crystallization processes such as: rapid thermal annealing (RTA),rapid thermal processing (RTP), furnace annealing, lamp annealing, argonion laser annealing, excimer laser annealing (ELA), phase modulated ELA,sequential lateral solidification (SLS), and single area-excimer lasercrystallization (SA-ELC), metal induced crystallization (MIC), metalinduced lateral crystallization (MILC), and zone melt recrystallization(ZMR), among others.

Each device layer 308 may be deposited by any known conventionaldeposition means suitable for the material at issue, such as: PVD;filament evaporation; RF heating; electron beam; ion assisted electronbeam; sputtering; diode sputtering; magnetron sputtering; DC sputtering;bias sputtering; RF sputtering; CVD; thermal CVD; LPCVD; PECVD; APCVD;high-density plasma CVD (HDPCVD); electron cyclotron resonance PECVD(ECR-PECVD); low temperature PECVD (LTPECVD); metalorganic CVD (MOCVD);PVD; hot-wire CVD; sol gel; evaporation; molecular beam (MB)evaporation; ion-plating; electro-plating; dip-plating (dipping); andelectroless-plating; other coating processes, such as aLangmuir-Blodgett process, spin-coating, spray-coating, and roll-oncoating; printing; transfer; ink-jetting; and powder-jetting, amongothers.

There are fundamentally no limits on the thickness of these devicecoating layers. For example, each may be as thin as a few angstroms toseveral tens of microns thick.

While certain representative embodiments have been shown for purposes ofillustrating the wide variety of coating materials that may be used, itwill be apparent to those skilled in the art that other coatingmaterials not disclosed herein may be used without departing from thescope of the invention.

Resist Layer

The material selected for each resist layer 328, 340 utilized in an EDMmethod of the present invention may be chosen from a wide variety ofperturbation activated compounds whose general properties can betailored or influenced under suitable stimuli. In general, any compoundor system, be it organic or inorganic, can be designed such that itsenergy barrier can be reduced by application of radiation, microwave,light, heat, electric field, magnetic field, chemical catalyst,stress-tension-pressure, etc. Furthermore, this reduction in energybarrier on exposure to an appropriate stimuli may produce a change in:resistance, conductance, capacitance, dielectric constant, chargeretention, refractive index, n surface reflection, light absorption,transmission and scattering, differential wetting and sorption, magneticsusceptibility, chemical solubility, polymerization, photo crosslinking, photobleaching, photostratification, amount of corrosion,crystallization and height, among others. Systems and chemical compoundsthat utilize these characteristics can therefore be used as a means tocreate patterned surfaces and relief structures.

Such systems and compounds include, but not limited too, the following:light- or radiation-based resist compositions and systems such as:photoresist, both positive and negative, wet film and dry film,chemically amplified resist, positive and/or negative electrodepositablephotoresist, electrophoretic photoresist, crystallization photoresist(PR), spin-coated liquid photoresist (LPR), acrylate monomers,isobornylmethacrylate, stilbenedimethacrylate, holographicphotopolymers, single and multicolor photopolymers compositions, colorfilms, photosensitive emulsions, halide emulsions, silver halides,photoetchable glass, germanosilicate glass, TiO₂ (photocatalysis intitanium oxides and sub oxides), photoactivation in polymethylsilane(PPMS), organotellurium, and selenium, among others; single ormultiplayer polymeric layer systems that undergo 2-level 3 dimensionalcrosslinking process, with oleophilic polymers and a photothermalconverter which converts radiation to heat and crosslinked hydrophilicpolymers; chacogenide glasses and compositions that exhibit phase changeand photorefractive effects, such as, amorphous As—S, As—Se and As—S—Sefilms, GexSbyTez, GeSbTe or InAgSbTe; thermal inorganic resistcompositions and systems, such as, heat and humidity induced corrosionin iron, calcium and aluminum films, among others; selective oxidationof amorphous hydrogenated silicon surface by removal of hydrogenpassivation under heat or light; structuring of aluminum films bylaser-induced corrosion in water; fractional change in aluminum oxide,iron oxide, or silver composition upon selective heating of therespective material on a thick amorphous carbon film; bismuth/indium andother bi- and tri-metallic alloying thermal resist; and in-situoxidation of nanometer sized transition metal clusters or colloids ofmetals of groups 4, 5, 6, 7 8, 9, 10, 11, or 12 of the periodic table,their metal oxides or metal sulfide analogues, among others.

The chosen resist type, be it photoresist, thermal resist orphotoactivable compound, may be deposited using any of the conventionalprocesses typically used in the semiconductor and printed circuit boardmicroelectronics industries. Such processes include: spin coating, spraycoating, meniscus coating, roller, curtain or extrusion coating, plasmadeposition, flash evaporation of monomers or polymers,electro-deposition or electrophoretic deposition, ink jet printing,screen printing, dispensing and blading, gravure, flexo-printing, anddrop-on-demand ink jet printing, among others. Inorganic resist systemsmay be deposited using techniques such as: PVD; filament evaporation; RFheating; electron beam; ion assisted electron beam; sputtering; diodesputtering; magnetron sputtering; DC sputtering; bias sputtering; RFsputtering; CVD; thermal CVD; LPCVD; PECVD; APCVD; HDPCVD; ECR-PECVD;LTPECVD; MOCVD; PVD; hot-wire CVD; sol gel; evaporation; molecular beam(MB) evaporation; ion-plating; electro-plating; dip-plating (dipping);and electroless-plating; other coating processes, such as aLangmuir-Blodgett process, spin-coating, spray-coating, and roll-oncoating; printing; transfer; ink-jetting; and powder-jetting, amongothers.

In lieu of a single resist layer coating, two or more resist layercoatings may be deposited on top of each other to form a stacked resistlayer. As mentioned above, each coating of a stacked resist may providean imaging level, i.e., a planar level within the resist layer that isparallel with the surface of the resist layer and that contains or willcontain a image that is independent and distinct from each other imagewithin the resist layer. The multiple resist layer coatings within aresist layer may be, e.g., similar or different in composition, or inthe manner in which they are activated, or the wavelengths at which theyare activated. Alternatively, as discussed below in more detail in thesection titled “Lithography Techniques”, a single resist coating maycontain two or more imaging levels when special lithography techniquesare utilized.

There are fundamentally no limits on the thickness of each resist layer328, 340. For example, each may be as thin as a few angstroms to severaltens of microns thick depending on choice and composition of the resist,resolution desired and activation schemes.

While certain representative embodiments have been shown for purposes ofillustrating the wide variety of resist materials and systems that maybe used, it will be apparent to those skilled in the art that otherresist materials not disclosed herein may be used without departing fromthe scope of the invention.

Protective Layers

As mentioned above, protective layers 336, 344 might be used, ifdesired, to protect the outer surfaces of corresponding respectiveresist layers 328, 340 during subsequent processing, as well as to serveas a second (temporary) substrate during such processing. Eachprotective layer 336, 344 may be made up on any of the materialsoutlined above for temporary substrate 300, but, of course, may bedifferent or identical in composition to the composition of thetemporary substrate chosen.

Bonding of Protective Substrate to Resist Layer

If one or both of protective layers 336, 344 are used, each may beattached to the corresponding respective resist layer 328, 340 in anysuitable one of a variety of ways including, but not limited to:chemical bonding using epoxies, adhesive, RTV, silicones, urethanes,etc. These materials may be water- or solvent-soluble epoxies, adhesive,etc., and may be cured/activated using plasma, light, UV, temperature,pressure, or anaerobic environment, among other things. Bonding may alsobe initiated by surface treatments using chemicals, activated plasmatreatments and vacuum processes, among others. Bonding processes mayalso be of a variety of types include, but not limited to microwave,anodic, fusion, adhesive, eutectic, resist, solder, thermo-compressionand/or low temperature glass, among others.

While certain representative embodiments have been shown for purposes ofillustrating a point, it will be apparent to those skilled in the artthat bonding methods not disclosed herein may be used without departingfrom the scope of the invention.

Techniques for Detaching Electronic Device Layer Stack from TemporarySubstrate

As discussed above, at a certain point in EDM method 200 (FIGS. 2A-B) itmay becomes desirable or necessary to remove temporary substrate 300from electronic device layer stack 304. If so, removal of temporarysubstrate 300 may be performed in any one of a number of ways, e.g.,providing a suitable impulse or number of impulses so as to initiate andmaintain a detaching front using one or more appropriate energy sources.Examples of such energy sources include, but are not limited to, amechanical source, a chemical source, a radiation source, an electricalsource and a thermal sink or source, among others. In addition,temporary substrate 300 may be subjected to stress, strain, shear,tension and/or other forms of mechanical, chemical, electrical,radiation treatments during or prior to initiating detaching of thesubstrate from device layer stack 304 to help facilitate/expedite theseparation action. This form of “treatment” also helps in isolating anddemarking the selected separation plane. These separating impulses maybe imparted in a flood, time-varying, spatially varying or continuousmanner.

Generally, a mechanical source for initiating and continuing separationof temporary substrate 300 from device layer stack 304 may utilizerotational, translational, compressional, expansional, and/or ultrasonicenergy, to impart mechanical separating action. Examples of suitablemechanical separating actions include, but are not limited to, grinding,tearing, scouring, abrading, and slicing, that may be imparted usingmechanical knives, saws, wire and muck saws, pressurized liquids andgases that act as directional chisels, hammers, among other things. Themechanical action can be introduced in a flood, time-varying, spatiallyvarying or continuous manner.

In a more particular example, a pressurized fluid jet, which acts withcompressional energy, can be used to perform the detaching process. Thefluid jet (or liquid jet or gas jet) impinges on a selected interfaceregion of temporary substrate 300/release layer 324 and device layerstack 304 so as to initiate the separation process and to separate thetwo into two distinct entities using a force, e.g., mechanical, chemicaland/or thermal force. One entity is temporary substrate 300, which isessentially unaffected by the removal and can be reused, and the otherentity is device layer stack 304 along with resist layer 328. Dependingon the application, the fluid jet can be adjusted in direction, locationand magnitude so as to achieve the desired separation effect. The fluidjet can be a liquid jet or a gas jet or a combination of liquid and gas.

A chemical source for initiating and continuing separation of temporarysubstrate 300 from device layer stack 304 can be selected fromparticles, fluids, gases, or liquids. These sources have chemistriesthat increase stress in the interface region. Examples of processes theutilize chemical action include, but are not limited to: wet chemicaletching; dry etching processes such as reactive ion etching (RIE);plasma/planar etching; plasma-enhanced (PE) etching; inductively coupledplasma (ICP) etching; deep reactive ion etching (DRIE); sputtering; ionenhanced etching; ion beam milling; chemically assisted ion beammilling; electron cyclotron resonance (ECR) plasma etching; high-densityplasma (HDP) etching; microwave and RF plasma assisted etching; andlaser induced/assisted chemical etching, among others. The chemicalsource may be introduced in a flood, time-varying, spatially varying orcontinuous manner.

An electrical source for initiating and continuing separation oftemporary substrate 300 from device layer stack 304 can be selected froman applied voltage or an applied electromagnetic field, each of whichmay be introduced in a flood, time-varying, spatially varying, orcontinuous manner. An example of implementing an electrical source iselectro-etching.

A thermal source or sink for initiating and continuing separation oftemporary substrate 300 from device layer stack 304 may operate usingradiation, convection or conduction. The thermal source may be selectedfrom a group comprising, among other things, a photon beam, microwaveradiation, a fluid jet, a liquid jet, a gas jet, an electro/magneticfield, an electron beam, a thermo-electric heating and a furnace. Thethermal sink may be selected from a group comprising, among otherthings, a fluid jet, a liquid jet, a gas jet, a cryogenic fluid, asuper-cooled liquid, a thermoelectric cooling means and anelectro/magnetic field. This thermal source can be applied in a flood,time-varying, spatially varying or continuous manner. Examples ofthermal source based separating processes include laser slicing based onmelting of material, microwave melting and slicing of material,gasifying, sublimating and decomposing the sacrificial layer, amongothers.

Still further, any of the above embodiments can be combined or evenseparated, depending on the application. As will be appreciated by thosehaving ordinary skill in the art, the type(s) of source(s) used willalso depend upon the application. In addition, it is noted that theselected impulse energy may be placed near or at an edge or cornerregion of the selected depth of the separation interface or releaselayer 324 or, alternatively, it may be placed at the center or any otherlocation along the selected depth of the interface.

It is noted that in some applications it may be desirable to leavetemporary substrate 300 “as is,” i.e., not separated from device layerstack 304. For example, if temporary substrate 300 is a metal or metalalloy, it could serve as an electrode, antenna, barrier coating forprotection against humidity or add to the mechanical strength of thelayered structure. If temporary substrate 300 is reasonably thin (say,<1 mm in thickness) it could be etched through during subsequentprocessing when the circuitry is defined. Alternatively, in someapplications it may be desirable to etch temporary substrate 300completely off, e.g., if its composition allows or if very highresolution lithography is required. Alternatively, in some applicationsit may be desirable to etch temporary substrate 300 only partially so asto utilize the temporary substrate properties as above, but also includethe option of high resolution lithography. Similarly, release layer 324may be etched off completely or only partially, depending on applicationand whether they can add any additional functionality to the finisheddevice.

While certain representative embodiments and details have been shown forpurposes of illustrating the invention, it will be apparent to thoseskilled in the art that various other separation methods exists and maybe used without departing from the scope of the invention, which isdefined in the appended claims.

Exposure Mechanism for Chosen Resist Material

As discussed above relative to resist layers 328, 340, the chosen resistsystem may be designed to have its energy barrier varied by theapplication of radiation, microwave, light, heat, electric field,magnetic field, chemical catalyst, stress-tension-pressure, etc. If alight source (i.e., radiation source) is chosen as the activation meansfor this reduction of energy barrier, the source may be a coherentsource (e.g., lasers) or an incoherent (e.g., lamps). Laser-basedsystems may use lasers that are continuous, pulsed, modulated, switchedor ultra-fast with micro-nano-femto second pulses. The laser/resistcombination might also be operated under 2-photon, 3-photon and othernon-linear regimes. In addition, the selected laser may be single lineor multi-line and may be a solid state, diode pumped solid state, gas,excimer, ion, or semiconductor laser, among others. The output of suchlaser may, e.g., be in the ultraviolet (UV), visible (VIS), nearinfrared (NIR), infrared (IR) or far infrared (FIR) part of thespectrum. Examples of incoherent light sources include UV, halogen,xenon and mercury arc lamps, among other broadband radiation sourcesthat may also be utilized. Note that lasers can also be sources ofincoherent radiation and are meant to be included as suitable incoherentsources.

It is noted that a multilayer resist technique, such as thin layerimaging (TLI), may be used as an alternative to single-layer resisttechnology. In TLI the uppermost layer of the resist is imaged, and thisimage is used to create an etch mask. The image is then developed usingan anisotropic RIE process. Alternatively, laser direct patterning(photo ablation) or laser micromachining techniques may be used toexpose and ablate each resist layer 328, 340, or perhaps even to patterndevice layer stack 304, if desired.

If a thermal source (physical heat source) is chosen as the activationmeans for this reduction of energy barrier, it may be take the form ofheated rollers, thermal pads, etc.

Resist layers 328, 340 may be exposed simultaneously ornon-simultaneously with the prescribed patterns needed for the type(s)of electronic devices to be made. The exposure may utilize eitherconventional masking technology or maskless techniques. Non-simultaneousexposures may be carried out sequentially at time T=1 on one surface,and time T=2 on the other surface, without moving the substrate or maskin relation to each other during this time T1 and T2. The exposure maybe carried out with resist layers 328, 340 oriented in a horizontalposition, a vertical position or at an intermediary angle. Furthermore,the exposure systems may incorporate a rotating drum or flat bedmachine.

It is understood that the intention of exposing resist layer 328, 340 isto create patterns in these layers that can then be transferred ontodevice layer stack 304. It is noted that there are physical means forachieving this transfer that are not dependant on resist exposure. Suchalternatives to resist exposure include, but are not limited to screenprinting, nano imprinting, nano stamping and micro imprinting. Thatlatter four all use the same basic technique in which a template is madewith relief structures in the shape and size of the patterns desired tobe transferred (either a positive template or a negative template). Thattemplate is then pressed, or “embossed,” into one of resist layers 328,340, thereby replicating the relief pattern in that resist layer. Thepattern is subsequently transferred into device layer stack 304 usingisotropic or anisotropic etching mechanisms.

While certain representative embodiments and details have been shown forpurposes of illustrating the invention, it will be apparent to thoseskilled in the art that various other exposure methods exists and may beused without departing from the scope of the invention, which is definedin the appended claims.

Lithography Techniclues

Conventional lithography techniques, such as projection, proximity,mirror projection and contact lithography, among others, may be used toimage a patterned mask onto resist layers 328, 340. In addition, newtechniques such as maskless lithography, variable magnificationprojection, automatic depth of focus correction and zone plate arraylithography, among others, may also be used. Furthermore, scanning modelithography, such as grating light valve (GLV) and digital lightprocessing (DLP) lithography may also be used. Scanning techniques mayinclude continuous scanning or step and scan and repeat techniques.Other techniques such as laser direct imaging (LDI) may also be used.

Depending on the needs of a particular application of an EDM method ofthe present invention, the mask used may be a monochrome binary mask,such as a conventional chrome or iron oxide mask which either allowlight to pass, or no light to pass through a given area. An exemplarymonochrome binary mask 400 is depicted in FIG. 4A. As shown in FIG. 4A,monochrome binary mask 400 either allows essentially all exposing light404 to pass or blocks essentially all of the exposing light, dependingupon whether or not a patterning material 408 is present. As shown inFIG. 4B, the mask 420 may alternatively be a gray scale mask, i.e., amask that allows any of essentially all exposing light 404 to pass,essentially no light to pass or some light to pass. This is accomplishedby depositing one or more patterning materials 424 in a pattern thatleaves, as desired, regions of mask 320 uncoated, regions coated so asto be largely non-transmission and regions coated so as to be partiallytransmissive to exposing light 404. As another alternative, as shown inFIG. 4C, the mask 440 used may be a color mask, which generally is amask having multicolor coatings 444 that each allow one color (e.g., afirst wavelength λ1) to pass, whereas a second color (e.g., a secondwavelength λ2 different from λ1) may or may not pass through a givenarea. Typically such a mask 440 would also have the option of notpassing any colors or all colors through a given area.

If a broadband light source or a multi line laser is used with a colormask, optical filters may be used between the light source and the maskto sequentially or simultaneously access the colors for the mask andreject others that will not be imaged. Alternatively, many single linesources (e.g., lasers) may be used inline simultaneously, or modulatedsequentially to allow one color or the other. Note that differentlithography methods may be mixed and match to create the desired effect.

One may realize the same result of patterning resist layers 328, 340 onboth facial sides of device layer stack 304 using a single- (or multi-)color maskless techniques. In addition, modulating/varying the intensityof the light source (laser) can provide an analog to the gray scalemask. Also, modulating/varying the wavelength of the light source(laser) can provide an analog to a color mask. Further,modulating/varying the light source (laser) intensity and wavelength canprovide an analog to a gray scale/color mask combination. Still,utilizing more than one light source (laser) having different wavelengthcan provide an analog to a color mask.

As mentioned above in the section titled “Resist Layer(s)”, a resistlayer may contain more than one imaging level. The various imaginglevels may be present in a single resist coating or among a plurality ofresist coatings that form a stacked resist layer. In the latter case,each resist coating may correspond respectively to one of the multipleimaging layers, as discussed in some of the examples presented below. Ingeneral, however, corresponding respective images may be formed on theseimaging layers using electromagnetic energy of different frequencies.FIG. 5 depicts typical absorption spectra 500, 510 of a resist material,respectively, prior to exposure at a wavelength and post exposure atthat wavelength. As is clearly evident, at a wavelength X, prior to theexposure of the resist material at that wavelength is highly absorbing.At that same wavelength X, post exposure the absorption coefficient ofthe material has reduced significantly. In other words, post exposurethe resist material is more transparent to wavelength X and theabsorption graph has blue shifted.

As depicted in FIG. 6C, a resist layer 600 made of such a resistmaterial may be imparted with different images 604, 608, 612 atdifferent depths within the layer, i.e., on different image levels 616,620, 624 by sequentially or simultaneously exposing the layer todifferent patterns using different wavelengths of electromagneticenergy. Referring now to FIGS. 6A-D, in FIG. 6A resist layer 600 mayexposed with electromagnetic energy having a wavelength λ=X so as toform a first image 604 on first image level 616. Once image level 616has been exposed, it is reasonably transparent to wavelength λ=X. Then,as shown in FIG. 6B, resist layer 600 may be exposed to electromagneticenergy having a wavelength λ=Y, wherein Y<X (i.e., wavelength Y isshorter than wavelength X), so as to form a second image 608 on secondimage level 620. Then, if desired, as shown in FIG. 6C a third image 612may be formed on third image level 624 by exposing resist layer 600 toelectromagnetic energy having a wavelength λ=Z, wherein Z<Y (i.e.,wavelength Z is shorter than wavelength Y). After resist layer 600 hasbeen developed, it may have the profile 628 shown in FIG. 6D.

It will be appreciated by those skilled in the art that the describedmethodology is a convenient way to perform gray scale lithography usingthe multiplexing nature of light. In this context, “multiplexing”implying the ability for an infinite number of wavelengths of light tocoexist at the same location at the same time and still maintain theirunique wavelength signatures.

FIG. 7 illustrates a dual-wavelength maskless direct layer writinglithography system 700 that may be used to simultaneously expose resistlayers 704, 708 having up to two imaging levels (not shown) as discussedabove. Lithography system 700 may be used for the exposure step(s) of anEDM method of the present invention, such as EDM system 200 of FIGS.2A-B. Indeed, several of the example recipes presented below indicatethe use of lithography system 700.

In this present example, lithography system 700 is configured forsimultaneous two sided exposure of the two resist layers 704, 708. Ofcourse, lithography system 700 could readily be modified for only singlesided exposure, if desired. In addition, it is noted that althoughlithography system 700 is set up for exposing two imaging layers usingtwo wavelengths, the system may be readily modified for exposing threeor more imaging layers using a corresponding number of wavelengths.Those skilled in the art will readily understand how to make suchmodifications.

Lithography system 700 may include first and second lasers 712, 716 eachcontrolled by a pattern generator, such as common pattern generator 720shown. Pattern generator 720 may be based on conventional patterngenerators, but with the modification that it produces patterns suitablefor the dual wavelength images imparted onto two imaging layers.Correspondingly, laser 712 may emit energy at a first wavelength λ1 andlaser 716 may emit energy at a second wavelength λ2 that is differentfrom first wavelength λ1 for the reasons discussed above. A pair ofbeamsplitters 724A-B and a set of mirrors 728A-C may be used to combinethe beams 732, 736 emitted from lasers 712, 716 and direct the combinedbeam 740 to each of the two resist layer 704, 708 as shown.

While certain representative embodiments and details have been shown forpurposes of illustrating the invention, it will be apparent to thoseskilled in the art that various other exposure and lithography methodsexists and may be used without departing from the scope of theinvention, which is defined in the appended claims.

Etching Device Layer Stack

As discussed above, device layer stack 304, resist layers 328, 340and/or protective layers 336, 344 may be removed, i.e., portions ofthese layers selectively removed by various removal techniques so as toform part or all of each electronic device made during a particularapplication of an EDM method of the present invention. Suitable ablatingtechniques include, but are not limited to wet and dry etching/millingtechniques and electromagnetic direct ablation, among others. Examplesof suitable dry etching techniques include RIE, plasma/planar etching,PE etching, ICP etching, DRIE, sputtering, ion enhanced etching, ionbeam milling, chemically assisted ion beam milling, ECR plasma, HDP,microwave and RF plasma assisted etching and laser induced/assistedchemical etching, among others. The chemical source may introduced in aflood, time-varying, spatially varying or continuous manner. An exampleof electromagnetic ablation is laser direct imaging, or photoablation.

While certain representative embodiments and details have been shown forpurposes of illustrating the invention, it will be apparent to thoseskilled in the art that other etching methods exists and may be usedwithout departing from the scope of the invention, which is defined inthe appended claims.

Laminating Permanent Substrate to Patterned Device Layer Stack

As discussed above, at a certain point during an EDM method of thepresent invention it may be desirable to laminate, or attach, apermanent substrate, such as permanent substrate 348, to patterneddevice layer stack 304. As also discussed above relative to temporarysubstrate 300 and protective layers 336, 244, there are many ways tobond two structure together. Depending, of course, on the type ofmaterial selected for permanent substrate 348, any one of the attachingtechniques described above relative to temporary substrate 300 andprotective layers 336, 344 may be used to secure the permanent substrateto device layer stack 304.

Passivation Materials

As discussed above, depending on the materials used for various layers,such as electronic device layers 308 and permanent substrate 348, it maybe desirable or necessary to provide device layer stack 304 withpassivation layer(s) 356 for isolating or otherwise protecting thedevice layers from unwanted environmental influences. The material(s)selected for passivation layer(s) 356 may be insulators or metalsdepending on the nature of passivation desired. For example, forisolating electronic structures such as TFTs, capacitors, etc., thepassivation materials are typically insulators. Any of theinsulator/metallic materials listed above relative to permanentsubstrate 300 can be deposited in thin or thick film form to function asa passivation layer.

Permanent Substrate

Generally, as discussed above, permanent substrate 348 is a permanentbacking substrate or platform for the finished circuitry sheet.Permanent substrate 348 may be transparent, opaque or translucent asneeded to suit a particular application. Materials suitable for use inpermanent substrate 348 include the materials listed above relative totemporary substrate 300. In addition to permanent substrate 348 itself,other functionality/functional layers may be built in or on thepermanent substrate prior to or after lamination to device layer stack304. For example: permanent substrate 348 may intrinsically acts as aplanarizing/barrier layer; scratch resistant layers may be deposited onor under the substrate; UV protection layers may be deposited on thesubstrate or incorporated within the composition of the substrate; colorfilters and black mask coatings may be deposited on the substrate; andmetallic edge seams/pixel seams for facilitating or allowing forhermetic bonding between the substrate and device layer stack 304 may bedeposited. The sealing may be induced by microwave bonding or otherconventional sealing method.

In addition, other coatings, such as chemical resiliency coatings,encapsulation coatings, anti-reflective coatings, anti-fingerprintcoatings, anti-static coatings, electrically conductive layers/coatings,anticorrosion layers, flame retardant coatings, adhesive layers,polarizing films, retardation films, or combinations thereof, amongothers may be deposited on permanent substrate 348, prior to or postlamination to device layer stack 304. These functional coating include,but are not limited to, organic or inorganic coatings.

While certain representative embodiments have been shown for purposes ofillustrating the wide variety of permanent substrates, it will beapparent to those skilled in the art that substrates not disclosedherein may be made without departing from the scope of the invention.

EXAMPLES

Following are a number of exemplary recipes for making active pixelmatrix circuitry sheets suitable for use in any of a variety of displayproducts. Each of these recipes utilizes various aspects of EDM method200 of FIGS. 2A-B. The steps in each of these recipes are selfexplanatory, with additional comments made for clarification or to pointout certain features of that recipe. It is noted that in each of theseexamples that include a corresponding set of figures, the stepdesignator corresponds alphabetically to the figure designator of therelevant figure in that set. For example, relative to Example 1 justbelow, Example 1 includes FIGS. 8A-8V, with FIG. 8A corresponding toStep A, FIG. 8B corresponding to Step B, FIG. 8C corresponding to StepC, and so on.

Example 1

Referring now to FIGS. 8A-8V, following is an exemplary recipe formaking a particular active matrix pixel circuitry sheet 800 (FIG. 8V) ofthe present invention that may be used as an active matrix backplane ofa display device.

-   Step A: Choose an aluminum metallic foil having a thickness of less    than about 20 microns as a temporary substrate 804.-   Step B: Attach a stiffener 808 to the backside of temporary    substrate 804. For example, stiffener 808 may be a nickel, stainless    steel or other metal foil having a thickness of about 100-200    microns.-   Step C: Electro-polish the exposed surface of aluminum foil    temporary substrate 804 so as to achieve a high degree of    planarization of surface 810.-   Step D: Deposit a gate metal layer 812. Alternatively, aluminum foil    temporary substrate 804 may be alloyed and intrinsically used as a    gate metal layer.-   Step E: Deposit a silicon nitride (SiNx) layer (coating) 816, an    amorphous hydrogenated silicon layer 820 and an n+ doped amorphous    silicon layer 824 using PECVD, sequentially without breaking vacuum    so as to form a device layer stack 826. The thickness of these    materials can be varied according to the particular application.-   Step F: Deposit a source/drain (S/D) and metal interconnect layer    828, preferably without breaking vacuum.-   Step G: Deposit a resist layer 832 on top of metal layer 828.-   Step H: Laminate a protective, peelable (or water soluble, UV    detachable, etc.) protective polymer sheet (layer) 836 on the free    surface of resist layer 832.-   Step I: Detach stiffener 808 (FIG. 8H).-   Step J: Deposit resist layer 840 on free surface of aluminum foil    temporary substrate 804.-   Step K: Laminate a protective, peelable (or water soluble, UV    detachable, etc.) protective polymer sheet 844 on free surface of    resist layer 840.-   Step L: Expose resist layers 832, 840 simultaneously using    conventional contact lithography and binary masks 846A-B.-   Step M: Develop resist layer 832 so as to impart pattern 848 shown.-   Step N: Etch source/drain, metal interconnect layer 828 as shown    using suitable wet or dry etching techniques.-   Step O1: Etch n+ doped amorphous silicon layer 824 (ohmic contact)    using dry etching.

Typically during this step, hydrogenated amorphous silicon layer 820 isalso partially etched. Metal layer 828 acts as a stop to inhibit anyetching of materials underneath it.

-   Step O2: Remove any remaining portions of resist layer 832 (FIG.    O1).-   Step P: Optionally, deposit passivation layer 852.-   Step Q1: Secure a permanent substrate 856 to the surface of device    layer stack 826. Note that the securing agent 858 (epoxy, adhesive,    etc.) will flow into the etched n+ doped groove and act as an    intrinsic passivation layer. The choice of securing agent can be    dictated by considering this secondary function.-   Step Q2: Develop resist layer 840 so as to impart pattern 860 shown.    FIG. Q3 is an overlay 884 illustrating (lower) pattern 860 in proper    registration with (upper) pattern 848. Overlay 884 shows four TFT    regions 888 each including a corresponding respective gate region    890 and source/drain regions 892.-   Step R: Etch the gate metal definition from metal layer 812.-   Step S: Etch underlying SiNx insulator layer 816, hydrogenated    amorphous silicon layer 820, and n+ doped amorphous silicon layer    824 until the underside of metal layer 828 is reached. Generally,    this step completes the formation of the structure of the TFTs 864    (only one of which is shown for convenience) within device layer    stack 826.-   Step T: Deposit indium-tin-oxide (ITO) layer 868 as shown.-   Step U: Pattern and etch ITO layer 868 as required so as to define    pixel electrodes 872.-   Step V: Deposit a passivation layer 876 over gate metal layer 812,    if desired. However, surface oxidation of aluminum/aluminum alloy    (or whatever metal is chosen for gate metal) may provide adequate    protection.

Regarding Example 1, the following points are noted:

-   1. Aluminum has a melting point of >650° C. and will easily    withstand the PECVD deposition temperature typically used in    conventional display manufacturing (<450° C.).-   2. In lieu of aluminum foil being used for temporary substrate 804,    as already described in an earlier section of this disclosure, very    thin stainless or other steel, nickel, metal or polyimide sheets may    be used.-   3. All patterning of the most critical layers of TFT 864 was    effectively performed at one time. Note that device layers 816, 820,    824, 828 may be deposited in reverse order (upside down stack) and    still yield the same results. That is, deposit S/D metal layer 828    first, n+ doped silicon layer 824 second, hydrogenated amorphous    silicon layer 820 third and silicon nitride layer 816 third, and    then gate metal layer 812. Of course, the mask positions will need    to be reversed, as well.-   4. It should be apparent to those skilled in the art that    projection/proximity lithography may readily be substituted for the    contact lithography shown. In addition, maskless amplitude scanning    lithography techniques may also be substituted for the binary masks    illustrated.-   5. This recipe utilizes a single coating resist layer 832, 840 on    each side of device layer stack 826. Each ITO pixel electrode 872    can be readily patterned and etched using only coarse    photolithography registration.-   6. Silicon dioxide and silicon nitride are commonly used as    passivation materials in the display/electronics industry.-   7. Note that the electro-optical material for the front plane (e.g.,    liquid crystal, OLED/PLED material, electrophoretic material,    electrochromic material, etc.) will be on ITO layer 868.-   8. As those skilled in the art will appreciate, this configuration    can use a storage-capacitor-on-gate design, or, alternatively, an    independent storage capacitor can be made with metal or ITO    deposition. This capacitor (not shown) may be deposited after the    passivation Step P, and before securing permanent substrate.-   10. Resist layer 840 could have been developed first, subsequently    etched and laminated to the permanent substrate 856 prior to    developing resist layer 832 and etching device layer stack 826 using    resist layer 832. In this case, ITO layer 868 and the electro    optical material would end up on the top surface in a manner similar    to conventional designs.-   11. The recipe of Example 1 allows for the TFT backplane to be    transmissive or opaque. This is dictated by the spectral    characteristics of the permanent substrate chosen.

Example 2

The recipe detailed in Example 1 may be modified for display devicesthat do not require a transparent TFT backplane. For example,self-emissive devices such as top emitting OLEDs/PLEDs, or reflectivedevices like electrophoretics, electrochromics, reflective LCDs do notrequire a backlight for operation. An exemplary modified recipe is asfollows. It is noted that steps A-L in the following recipe areidentical to Steps A-L revealed in Example 1, above. The following stepsare illustrated in corresponding respective FIGS. 9A-9V.

-   Step A: Choose an aluminum metallic foil having a thickness of less    than about 20 microns as a temporary substrate 900.-   Step B: Attach a stiffener 904 to the backside of temporary    substrate 900. For example, stiffener 904 may be a nickel, stainless    steel or other metal foil having a thickness of about 100-200    microns.-   Step C: Electro-polish the exposed surface of aluminum foil    temporary substrate 900 so as to achieve a high degree of    planarization on surface 906.-   Step D: Deposit a gate metal layer 908. Alternatively, aluminum foil    temporary substrate 900 may be alloyed and intrinsically used as a    gate metal layer.-   Step E: Deposit a silicon nitride (SiNx) layer 912 (coating), an    amorphous hydrogenated silicon layer 916 and an n+ doped amorphous    silicon layer 920 using PECVD, sequentially without breaking vacuum.    The thickness of these materials can be varied as required for each    application.-   Step F: Deposit a source/drain (S/D) and metal interconnect layer    924, preferably without breaking vacuum.-   Step G: Deposit a resist layer 928 on top of metal layer 924.-   Step H: Laminate a protective, peelable (or water soluble, UV    detachable, etc.) protective polymer sheet 932 on free surface of    resist layer 928.-   Step I: Detach stiffener 904 (FIG. 9H).-   Step J: Deposit a resist layer 936 on the free surface of aluminum    foil temporary substrate 900.-   Step K: Laminate a protective, peelable (or water soluble, UV    detachable, etc.) protective polymer sheet 940 on free surface of    resist layer 936.-   Step L: Expose resist layers 928, 936 simultaneously using    conventional contact lithography and binary masks 942-A-B.-   Step M: Develop resist layer 936 so as to impart pattern 944 shown.-   Step N: Etch the gate metal definition into metal layer 908.-   Step 0: Secure a permanent substrate 948 over metal layer 908 using    an epoxy 950.

Epoxy 950 may act as a passivation layer for the gate metal, ifrequired.

-   Step P1: Develop resist layer 928 so as to impart pattern 952 shown.    FIG. P2 is an overlay 976 illustrating (lower) pattern 952 in proper    registration with (upper) pattern 944. Overlay 976 shows four TFT    regions 980 each including a corresponding respective gate region    984 and source/drain 988 regions, with one of each of the    source/drain regions of each TFT region being integral with pixel    electrode region 990.-   Step Q: Etch S/D and metal interconnect layer 924 as shown using wet    etching or dry etching techniques. Etch n+ doped amorphous silicon    layer 920 (ohmic contact) by dry etching. (Typically, during this    step hydrogenated amorphous silicon layer 916 is also partially    etched). Metal layer 924 acts as a stop to inhibit etching of    materials underneath it.-   Step R: Remove any remaining portions of resist layer 928 (FIG. 9Q).-   Step S: Deposit a passivation layer 956, such as an SiNx or SiO₂    layer.-   Step T: Deposit a conductor layer 960 on top of passivation layer    956 (e.g., ITO, metal, etc.)-   Step U: Pattern conductor layer 960 into pixel electrodes 964.-   Step V: Deposit/fill an electro-optical material 968 over the pixel    electrodes 964.

The recipe outlined immediately above allows for the fabrication of anopaque TFT backplane. A driven pixel electrode design that uses aparallel plate capacitor may be made using this recipe. Such a designmay be used for TFT backplanes for reflective LCD, top emissiveOLED/PLED, electrophoretics and electrochromic displays, among others.Since these types of displays do not use a backlight and, consequently,there is no light transmitted from the front side onto hydrogenatedamorphous silicon layer 916 underneath the drain metal segments, thereis no issue with photo-induced leakage current problems with the TFTs972 (FIG. 9V) of this recipe.

Example 3

The recipe detailed in Example 2 may be further modified for displaysthat do not require a transparent TFT backplane. An exemplary modifiedrecipe is as follow. It is noted that Step A-L in the following recipeare identical Steps A-L revealed in each of Examples 1 and 2, above.FIGS. 10A-10U illustrate the following corresponding respective steps.

-   Step A: Choose an aluminum metallic foil having a thickness of less    than about 20 microns as a temporary substrate 1000.-   Step B: Attach a stiffener 1004 to the backside of temporary    substrate. For example, stiffener may be a nickel, stainless steel    or other metal foil having a thickness of about 100-200 microns.-   Step C: Electro-polish the exposed surface of aluminum foil    temporary substrate 1000 so as to achieve a high degree of    planarization on surface 1006.-   Step D: Deposit a gate metal layer 1008. Alternatively, aluminum    foil temporary substrate 1000 may be alloyed and intrinsically used    as a gate metal layer.-   Step E: Deposit a silicon nitride (SiNx) layer 1012 (coating), an    amorphous hydrogenated silicon layer 1016, and an n+ doped amorphous    silicon layer 1020 using PECVD, sequentially without breaking    vacuum. The thickness of these materials can be varied to suit each    application.-   Step F: Deposit a source/drain (S/D) and metal interconnect layer    1024, preferably without breaking vacuum.-   Step G: Deposit a resist layer 1028 on top of metal layer 1024.-   Step H: Laminate a protective, peelable (or water soluble, UV    detachable, etc.) protective polymer sheet 1032 on free surface of    resist layer 1028.-   Step I: Detach stiffener 1004 (FIG. 10H).-   Step J: Deposit resist layer 1036 on the free surface of aluminum    foil temporary substrate 1000.-   Step K: Laminate a protective, peelable (or water soluble, UV    detachable, etc.) protective polymer sheet 1040 on free surface of    resist layer 1036.-   Step L: Expose resist layers 1028, 1036 simultaneously using    conventional contact lithography and binary masks 1042A-B.-   Step M: Develop resist layer 1028 so as to impart pattern 1044    shown. Note that pattern 1044 is identical to pattern 944 of Example    2, above.-   Step N1: Etch S/D and metal interconnect layer 1024 as shown using    wet etching or dry etching techniques. This step forms the pixel    electrodes 1046.-   Step N2: Etch n+ doped amorphous silicon layer 1020 (ohmic contact)    by dry etching. (Typically, during this step hydrogenated amorphous    silicon layer 1016 is also partially etched). Metal layer 1024 acts    as a stop to inhibit any etching of materials underneath it.-   Step O: Remove any remaining portions of resist layer 1028 (FIG. 10N    2).-   Step P: Optionally, deposit a passivation layer 1048, e.g., an SiNx    or SiO₂ layer.-   Step Q: Secure a permanent substrate 1052 to passivation layer 1048,    if provided, or to metal layer 1024, e.g., using an epoxy 1050.    Epoxy 1050 can act as a passivation layer for metal layer 1024 if    required.-   Step R1: Develop resist layer 1036 so as to impart pattern 1056    shown. Note that pattern 1056 is identical to patterns 860, 952 used    in Examples 1 and 2, respectively. FIG. R2 is an overlay 1072    illustrating (lower) pattern 1036 in proper registration with    (upper) pattern 1028. Overlay 1072 shows four TFT regions 1076 each    including a corresponding respective gate region 1080 and    source/drain regions 1084, with one of each of the source/drain    regions of each TFT region being integral with a corresponding pixel    electrode region 1088.-   Step S: Etch the gate metal definition into metal layer 1008. Etch    the underlying SiNx insulation layer 1012, hydrogenated amorphous    silicon layer 1016 and n+ doped amorphous silicon layer 1020 until    the underside of the S/D and electrode pixel metal layer 1024 is    reached.-   Step T: Deposit a passivation layer 1060 over gate metal layer 1008,    if required. Pattern passivation layer 1060.-   Step U: Deposit/fill an electro-optical material 1064 on top of    pixel electrodes 1046.

Similar to Example 2, above, the recipe just outlined allows for opaqueTFT backplane. A driven pixel electrode design that uses a parallelplate capacitor may be made using this recipe. Such a design may be usedfor TFT backplanes for reflective LCD, top emissive OLED/PLED,electrophoretics and electrochromic displays, among others. Since thesetypes of displays do not use a backlight and, consequently, there is nolight transmitted from the front side onto the hydrogenated amorphoussilicon layer 1016 underneath the drain metal segments, there is noissue with photo-induced leakage current problems with the TFTs 1068.

The configuration of a circuitry sheet, such as circuitry sheet 1072 ofFIG. 10X, made using this recipe can use a storage-capacitor-on-gatedesign, or, alternatively, an independent storage capacitor can be madewith metal or ITO deposition. This capacitor (not shown) may bedeposited after the passivation Step P, and before securing permanentsubstrate 1052.

Example 4

The recipe detailed in Example 2, above, may be further modified fordisplays that do not require a transparent TFT backplane. An exemplarymodified recipe is as follows. It is noted that Step A-E of thefollowing recipes are identical to Steps A-E revealed in each ofExamples 1 and 2, above. FIGS. 11A-11V illustrate the followingcorresponding respective steps.

-   Step A: Choose an aluminum metallic foil having a thickness of less    than about 20 microns as a temporary substrate 1100.-   Step B: Attach a stiffener 1104 to the backside of temporary    substrate 1100. For example, stiffener 1104 may be a nickel,    stainless steel or other metal foil having a thickness of about    100-200 microns.-   Step C: Electro-polish the exposed surface of aluminum foil    temporary substrate 1100 so as to achieve a high degree of    planarization on surface 1106.-   Step D: Deposit a gate metal layer 1108. Alternatively, aluminum    foil temporary substrate 1100 may be alloyed and intrinsically used    as a gate metal layer.-   Step E: Deposit a silicon nitride (SiNx) layer 1112 (coating), an    amorphous hydrogenated silicon layer 1116 and an n+ doped amorphous    silicon layer 1120 using PECVD, sequentially without breaking    vacuum. The thickness of these materials can be varied, as is    application specific.-   Step F: Deposit an ITO layer 1124, preferably without breaking    vacuum utilized in Step E.-   Step G: Deposit source/drain (S/D) and metal interconnect layer    1128, preferably without breaking vacuum utilized in Steps F and G.-   Step H: Deposit resist layer 1132 on top of metal layer 1128.-   Step I: Laminate a protective, peelable (or water soluble, UV    detachable, etc.) protective polymer sheet 1136 on free surface of    resist layer 1132.-   Step J: Detach stiffener 1104 (FIG. 11I).-   Step K: Deposit a resist layer 1140 on the free surface of aluminum    foil temporary substrate 1100.-   Step L: Laminate a protective, peelable (or water soluble, UV    detachable, etc.) protective polymer sheet 1144 on free surface of    resist layer 1140.-   Step M: Expose resist layers 1132, 1140 simultaneously using    conventional contact lithography and binary masks 1146A-B.-   Step N: Develop resist layer 1132 so as to impart pattern 1148    shown. Note that pattern 1148 is identical to patterns 944, 1044    used in Examples 2 and 3, respectively.-   Step O1: Etch metal layer 1128 using wet etching or dry etching    techniques.-   Step O2: Etch through ITO layer 1124 using dry or wet etching    techniques so as to define the pixel electrodes 1150.-   Step 03: Etch n+ doped amorphous silicon layer 1120 (ohmic contact)    by dry etching. (Typically, during this step the hydrogenated    amorphous silicon layer 1116 is also partially etched). Metal layer    1128 acts as a mask to inhibit any etching of materials underneath    it.-   Step P: Remove any remaining portions of resist layer 1132 (FIG.    1103).-   Step Q: Optionally, deposit a passivation layer 1152, e.g., an SiNx    or SiO₂.-   Step R: Secure a permanent substrate 1156 to passivation layer 1152,    if provided, or to metal layer 1128, e.g., using an epoxy 1158.    Epoxy 1158 can act as a passivation layer for metal layer 1128 if    required.-   Step S1: Develop resist layer 1140 using the mask pattern 1160    shown. Note that mask pattern 1160 is identical to mask patterns    860, 952 used in Examples 1 and 2, respectively. FIG. S2 is an    overlay 1172 illustrating (lower) pattern 1160 in proper    registration with (upper) pattern 1148. Overlay 1172 shows four TFT    regions 1176 each including a corresponding respective gate region    1180 and source/drain 1184 regions, with one of each of the    source/drain regions of each TFT region being integral with pixel    electrode region 1188.-   Step T: Etch the gate metal definition into metal layer 1108. Etch    underlying SiNx insulating layer 1112, hydrogenated amorphous    silicon layer 1116 and n+ doped amorphous silicon layer 1120 until    the underside of ITO layer 1124 is reached.-   Step U: Deposit a passivation layer 1164 over gate metal layer 1108,    if required. Pattern passivation layer 1164. Step V: Deposit/fill an    electro-optical material 1168 over pixel electrodes 1150.

Similar to Example 2, above, the recipe just outlined allows for thecreation of opaque TFT backplanes. A driven pixel electrode design thatuses a self-aligned and patterned ITO layer may be made using thisrecipe. Such a design may be used for TFT backplanes for reflective LCD,top emissive OLED/PLED, electrophoretics and electrochromic displays,among others. Since these types of displays do not use a backlight and,consequently, there is no light transmitted from the front side onto thehydrogenated amorphous silicon layer 1116 underneath the drain metalsegments, there is no issue with photo-induced leakage current problemswith the TFTs.

The configuration of a circuitry sheet made using this recipe, such ascircuitry sheet 1172 of FIG. 11X, can use a storage-capacitor-on-gatedesign, or, alternatively, an independent storage capacitor can be madewith metal or ITO deposition. This capacitor (not shown) may bedeposited after the passivation Step Q, and before securing permanentsubstrate 1156. Alternatively, the capacitor may be deposited after thedepositing and patterning passivation layer 1164.

Example 5

One potential shortcoming with a TFT backplane made using the recipe ofExample 1 is the possible presence of an unetched layer of hydrogenatedamorphous silicon under the gate metal lines. Since hydrogenatedamorphous silicon is a photoconductive material, if such a TFT backplaneis utilized in a transmission system having a backlight, as would be thecase, e.g., in a backlight illuminated transmission LCD display, itcould pose anomalous switching problems and leakage currents within theTFT switch. In this connection, FIG. 12 shows an overlay 1200 of themask patterns 848, 860 of Example 1 (FIGS. 8M and 8Q2). In overlay 1200,mask pattern 848 defines source/drain regions 1204A-B and data bus lines1208, and mask pattern 860 defines gate metal regions 1212 and gate buslines 1216. Overlay 1200 highlights the regions 1220 under the gate buslines 1216 that may not get entirely etched. The following recipedetailed in Example 5 depicts a methodology that can convenientlyeliminate this problem. FIGS. 13A-13AB illustrate the followingcorresponding respective steps.

-   Step A: Choose an aluminum metallic foil having a thickness of less    than about 20 microns as a temporary substrate 1300.-   Step B: Attach a stiffener 1304 to the backside of temporary    substrate 1300. For example, stiffener 1304 may be a nickel,    stainless steel or other metal foil having a thickness of about    100-200 microns.-   Step C: Electro-polish the exposed surface of aluminum foil    temporary substrate 1300 so as to achieve a high degree of    planarization on surface 1306.-   Step D: Deposit a gate metal layer 1308. Alternatively, aluminum    foil temporary substrate 1300 may be alloyed and intrinsically used    as a gate metal layer.-   Step E: Deposit a silicon nitride (SiNx) layer 1312 (coating), an    amorphous hydrogenated silicon layer 1316 and an n+ doped amorphous    silicon layer 1320 using PECVD, sequentially without breaking    vacuum. The thickness of these materials can be varied according to    the specific application.-   Step F: Deposit source/drain (S/D) and metal interconnect layer    1324, preferably without breaking vacuum utilized in Step E.-   Step G: Deposit resist layer coating 1328A over metal layer 1324.-   Step H: Deposit resist layer coating 1328B onto resist layer coating    1328A.-   Step I: Laminate a protective, peelable (or water soluble, UV    detachable, etc.) protective polymer sheet 1332 on free surface of    resist layer coating 1328B.-   Step J: Detach stiffener 1304 (FIG. 13I).-   Step K: Deposit a resist layer 1336 on the free surface of temporary    substrate 1300.-   Step L: Laminate a protective, peelable (or water soluble, UV    detachable, etc.) protective polymer sheet 1340 on free surface of    resist layer 1336.-   Step M: Expose resist layer coatings 1328A-B and resist layer 1336    simultaneously using a dual-wavelength maskless lithography/direct    laser writing lithography.

Note that resist layer coating 1328A differs in composition or spectralresponse from resist layer coating 1328B. Also, resist layer coating1328B is reasonably transparent to the wavelength (be it λ1 or λ2 inFIG. 7) that will be absorbed by resist layer coating 1328A. Resistlayer 1336 may be identical in composition or spectral response toresist layer coating 1328A or resist layer coating 1328B.

-   Step N: Develop resist layer coating 1328B. Note the imparted    pattern 1344 of this coating.-   Step O1: Etch resist layer coating 1328A as shown using wet etching    or dry etching techniques.-   Step O2: Etch metal layer 1324, n+ doped amorphous silicon layer    1320 and hydrogenated amorphous silicon layer 1316 all the way down    to the top of silicon nitride layer 1312. (This step ends up    removing photoconductive amorphous silicon layer 1316 under the gate    bus lines.)-   Step P: Remove any remaining portions of resist layer coating 1328B    (FIG. 13O 2).-   Step Q: Develop resist layer coating 1328A. Note that black exposed    regions of pattern 1346 will be left behind, and the hatched regions    will be removed during this developing stage.-   Step R: Etch metal layer 1324 to define S/D and metal interconnect    regions.-   Step S: Etch n+ doped amorphous silicon layer 1320 and partially    into hydrogenated amorphous silicon layer 1316.-   Step T: Remove any remaining portions of resist layer coating 1328A    (FIG. 13S).-   Step U: Optionally, deposit a passivation layer 1348, e.g., an SiNx    or SiO₂ layer.-   Step V: Secure a permanent substrate 1352 to passivation layer 1348,    if provided, or to metal layer 1324, e.g., using an epoxy 1354.    Epoxy 1354 can act as a passivation layer for metal layer 1324 if    required.-   Step W1: Develop resist layer 1336 using mask pattern 1352. Note    that imparted pattern 1356 is identical to pattern 860 used in    Example 1 (FIG. 8Q 2). FIG. W2 is an overlay 1380 illustrating    (lower) pattern 1352 in proper registration with (upper) patterns    1344, 1346. Overlay 1380 shows four TFT regions 1384 each including    a corresponding respective gate region 1388 and source/drain 1392    regions, with one of each of the source/drain regions of each TFT    region being integral with pixel electrode region 1396.-   Step X: Etch gate metal definition into metal layer 1308.-   Step Y: Etch underlying SiNx insulator layer 1312, hydrogenated    amorphous silicon layer 1316 and n+ doped amorphous silicon layer    1320 until the underside of the S/D and electrode pixel metal layer    1324 is reached.-   Step Z: Deposit an ITO layer 1360 over gate metal layer 1308.-   Step AA: Pattern ITO layer 1360 so as to define pixel electrodes    1372.-   Step AB: Deposit/fill an electro-optical material 1376 on top of the    pixel electrodes 1372.

Regarding Example 5, the following points are noted:

-   1. Aluminum has a melting point of >650° C. and will easily    withstand the PECVD deposition temperature typically used in    conventional display manufacturing (<450° C.).-   2. In lieu of aluminum foil being used for temporary substrate 1300,    as already described in an earlier section of this disclosure, very    thin nickel or polyimide sheets may be used.-   3. All patterning of the most critical layers of TFT was effectively    performed at one time. Note that device layers 1312, 1316, 1320,    1324 may be deposited in reverse order (upside down stack) and still    yield the same results. That is, deposit S/D metal layer 1324 first,    n+ doped silicon layer 1320 second, hydrogenated amorphous silicon    layer 1316 third and silicon nitride layer 1312 fourth, and then    gate metal layer 1308. Of course, the mask positions will need to be    reversed as well.-   4. It is also apparent that projection/proximity/contact lithography    using a color mask or gray scale mask could readily be substituted    for the maskless technique shown.-   5. This recipe utilizes a two-coating resist layer 1328 on one    surface and one-coating resist layer 1336 on the other surface. The    ITO pixel electrodes 1372 can be patterned and etched readily and    only requires coarse photolithography registration.-   6. Note that electro-optical material 1376 for the front plane    (e.g., liquid crystal, OLED/PLED material, electrophoretic material,    electrochromic material, etc.) will be on ITO layer 1360.-   7. This configuration can use a storage-capacitor-on-gate design,    or, alternatively, an independent storage capacitor can be made with    metal or ITO deposition. This capacitor (not shown) may be deposited    after the passivation Step P, and before securing permanent    substrate 1352.-   8. Resist layer 1336 could have been developed first, and    subsequently etched and laminated to permanent substrate 1348. After    this, resist layer coatings 1328B, 1328A could have been developed    and the corresponding layers etched. In this case, ITO layer 1356    and electro-optical material 1364 would end up on the top surface in    a manner similar to conventional designs.-   9. The recipe of Example 5 allows for a TFT backplane that can be    used in a transmissive LCD and bottom emitting OLED/PLED displays    without any issues with photo induced leakage currents in the TFTs.    Of course, however, this recipe can produce a universally applicable    backplane and may also be used for reflective LCD, front emissive    OLED/PLED, electrophoretics and electrochromic displays, among    others.-   10. Basically, a trench defining the pixel region is created using    resist layer coating 1328B as a mask, and then the etch-back region    between the source and drain is defined and created using resist    layer coating 1328A as a mask. Passivation layer 1344 fills in this    trench and the source/drain region and creates a defining wall    within which the pixel region lies. An ITO or other transparent    conductive electrode material may be deposited in the trench,    potentially removing the need for patterning such layer entirely.-   11. The presence of a trench may be especially helpful when using a    conductive nanotube paste, which can be ink jet printed into the    pixel regions without any further need for patterning.-   12. It is apparent that using more than resist coating per surface    provides additional degrees of freedom in manipulating the TFT    pattern.-   13. Additional examples include the use of two resist layer coatings    one surface and an additional two resist layer coatings on the other    surface such that a black matrix may be integrated surrounding the    pixel electrode region.-   14. Antenna elements can be constructed for RFID tags simultaneously    with TFT elements.-   15. PIN sensors for x-ray digital imaging sheets may be constructed    using the recipe of Example 5. In fact, the PIN coatings (p-doped    silicon and n-doped silicon) may be deposited after source/drain    metal layer 1324 and then isolated with one resist layer, with the    other resist layers on the other side used to create the TFTs.

Example 6

The recipe of this example is a variation on the recipe of Example 5. Inthis case, instead of a two-coating resist layer being used on one sideand a single-coating resist layer being used on the other, two-coatingresist layers are used on each side. This allows realization ofpatterned ITO pixel electrodes on one side while locating the permanentsubstrate on the other side. The recipe is as follows. FIGS. 14A-14ADillustrate the following corresponding respective steps.

-   Step A: Choose an aluminum metallic foil having a thickness of less    than about 20 microns as a temporary substrate 1400.-   Step B: Attach a stiffener 1404 to the backside of temporary    substrate 1400. For example, stiffener 1404 may be a nickel,    stainless steel or other metal foil having a thickness of about    100-200 microns.-   Step C: Electro-polish the exposed surface of aluminum foil    temporary substrate 1400 so as to achieve a high degree of    planarization of surface 1406.-   Step D: Deposit a gate metal layer 1408. Alternatively, aluminum    foil temporary substrate 1400 may be alloyed and intrinsically used    as a gate metal layer.-   Step E: Deposit a silicon nitride (SiNx) layer 1412 (coating), an    amorphous hydrogenated silicon layer 1416 and an n+ doped amorphous    silicon layer 1420 using PECVD, sequentially without breaking    vacuum. The thickness of these materials can be varied, as is    application specific.-   Step F: Deposit source/drain (S/D) and metal interconnect layer    1424, preferably without breaking vacuum utilized in Step E.-   Step G: Deposit an ITO layer 1428 onto metal layer 1424.-   Step H: Deposit a resist layer coating 1432A onto ITO layer 1428.-   Step I: Deposit a resist layer coating 1432B onto resist layer    coating 1432A.-   Step J: Laminate a protective, peelable (or water soluble, UV    detachable, etc.) protective polymer sheet 1436 on free surface of    resist layer coating 1432B.-   Step K: Detach stiffener 1404 (FIG. 14J).-   Step L: Deposit resist layer coating 1440A on the free surface of    aluminum foil temporary substrate 1400.-   Step M: Deposit resist layer coating 1440B onto resist layer coating    1440A.-   Step N: Laminate a protective, peelable (or water soluble, UV    detachable, etc.) protective polymer sheet 1444 on the free surface    of resist layer coating 1440B.-   Step O: Expose all resist layer coatings 1432A-B, 1440A-B    simultaneously using dual wavelength maskless lithography/direct    laser writing lithography (see FIG. 7).

Note that each of resist layer coatings 1432B, 1440B differs incomposition or spectral response from corresponding respectiveunderlying resist layer coatings 1432A, 1440A. Also, each of resistlayer coatings 1432B, 1440B is reasonably transparent to the wavelength(be it λ1 or λ2 in FIG. 7) that will be absorbed by correspondingrespective underlying resist layer coatings 1432A, 1440A. Resist coatinglayer 1432A may be identical to resist coating layer 1440A, and resistlayer coating 1432B may be equal to resist layer coating 1440B.

-   Step P: Develop resist layer coating 1440B. Note imparted pattern    1448.-   Step Q: Etch resist layer coating 1440A and gate metal layer 1408.-   Step R: Etch underlying SiNx insulator layer 1412, hydrogenated    amorphous silicon layer 1416, n+ doped amorphous silicon layer 1420    and S/D metal layer 1424 until the underside of ITO layer 1428 is    reached.-   Step S: Remove any remaining portions of resist layer coating 1440B    (FIG. 14R).-   Step T: Develop resist layer coating 1440A. Note imparted pattern    1452.-   Step U: Etch the gate metal definition into metal layer 1408.-   Step V: Deposit a passivation layer 1456.-   Step W: Deposit a pixel capacitor 1460 (opaque or transparent) and    pattern, if required.-   Step X: Secure a permanent substrate 1464 to passivation layer 1456,    if provided, e.g., using an epoxy 1466. Epoxy 1466 can act as a    passivation layer for gate metal layer 1408 if required.-   Step Y: Develop resist layer coating 1432B. Note imparted pattern    1468.-   Step Z1: Etch resist layer coating 1432A as shown using wet etching    or dry etching techniques.-   Step Z2: Etch metal layer 1424, n+ doped amorphous silicon layer    1420 and hydrogenated amorphous silicon layer 1416 all the way down    to silicon nitride layer 1412. (This step ends up removing    photoconductive amorphous silicon layer 1416 under the gate bus    lines.)-   Step AA: Remove any remaining portions of resist layer coating 1432B    (FIG. Z2).-   Step AB1: Develop resist layer coating 1432A. Note the black exposed    regions of imparted pattern 1470 will be left behind, and the    hatched regions will be removed during this developing stage. FIG.    14AB2 is an overlay 1480 illustrating (lower) patterns 1468, 1470 in    proper registration with (upper) patterns 1448, 1452. Overlay 1480    shows four TFT regions 1484 each including a corresponding    respective gate region 1488 and source/drain 1492 regions, with one    of each of the source/drain regions of each TFT region being    integral with pixel electrode region 1496. Etch metal layer 1424 to    define S/D and metal interconnect regions. Note that this etching    does not occur at the section shown in the drawings. See overlay of    FIG. AB2 for regions etched. Etch n+ doped amorphous silicon layer    1420 and partially into hydrogenated amorphous silicon layer 1416.    Remove any remaining portions of resist layer coating 1432A (FIG.    AB1).-   Step AC: Deposit and pattern a passivation layer 1472, e.g., an SiNx    or SiO₂ layer.-   Step AD: Deposit/fill an electro-optical material 1476 over pixel    electrode layer 1428.

The recipe of Example 6 allows for a TFT backplane that can be used in atransmissive LCD and bottom emitting OLED/PLED displays without anyissues with photo induced leakage currents in the TFTs. Of course,however, this recipe can produce a universally applicable backplane andmay also be used for reflective LCD, front emissive OLED/PLED,electrophoretics and electrochromic displays, among others.

Examples 7-12

Examples 1-6 above have detailed recipes using hydrogenated amorphoussilicon. It will be appreciated by those skilled in the art that hightemperature polysilicon or re-crystallized silicon may be substitutedfor the amorphous silicon. It is known that as-deposited polysiliconsuffers from high surface roughness, which has restricted its use forTFTs. High interfacial trap densities, leakage current issues and othersurface anomalies on insulator layers deposited on such rough siliconlayers have been identified as problematic issues. In a recentexperiment using as deposited high temperature polysilicon, the presentinventor observed that the top surface of the deposited polysiliconlayer was indeed very rough and scattered visible radiation. However,when the underside of that same layer was examined, it revealed a highlypolished surface. This surface was visually very polished, whichoptically indicates a very low surface roughness.

Consequently, Examples 7-12 are derived from corresponding respectiveExamples 1-6. In Examples 7-12, instead of depositing a hydrogenatedamorphous silicon layer on the silicon nitride layer, a polysiliconlayer is deposited on the silicon nitride layer. Clearly, thepolysilicon can be deposited directly onto the silicon nitride layer,thereby completely circumventing the issues that have restricted use ofas-deposited polysilicon for TFTs to date. In this case, the TFT-formingactive layers, i.e., the metal gate later, the insulator layer, and thepolysilicon layer, can be readily optimized for their properties. Itwill also be appreciated by those skilled in the art that otherrecrystallization techniques and other TFT structures, such as top gatestructures, may be readily implemented using EDM method 200 (FIGS.2A-B).

Example 13

Like the recipe of Example 6 above, the recipe of Example 13 utilizes atwo-coating resist layer on one side and a two-coating resist layer onthe other side. In this case, the use of these four resist layercoatings allows for the realization of patterned ITO pixel electrodes onone surface with a permanent substrate being secured to the othersurface. The recipe is as follows. FIGS. 15A-15AI illustrate thefollowing corresponding respective steps.

-   Step A: Choose an aluminum metallic foil having a thickness of less    than about 20 microns as a temporary substrate 1500.-   Step B: Attach a stiffener 1504 to the backside of temporary    substrate 1500. For example, stiffener 1504 may be a nickel,    stainless steel or other metal foil having a thickness of about    100-200 microns.-   Step C: Electro-polish the exposed surface of aluminum foil    temporary substrate 1500 so as to achieve a high degree of    planarization on surface 1506.-   Step D: Deposit a gate metal layer 1508. Alternatively, aluminum    foil temporary substrate 1500 may be alloyed and intrinsically used    as a gate metal layer.-   Step E: Deposit a silicon nitride (SiNx) layer 1512 (coating), an    amorphous hydrogenated silicon layer 1516, and an n+ doped amorphous    silicon layer 1520 using PECVD, sequentially without breaking    vacuum. The thickness of these materials can be varied, as is    application specific.-   Step F: Deposit source/drain (S/D) and metal interconnect layer    1524, preferably without breaking vacuum utilized in Step E.-   Step G: Deposit an ITO layer 1528 onto metal layer 1524.-   Step H: Deposit a passivation layer 1532 onto ITO layer 1528. (This    layer maybe inorganic or organic. Alternatively, the resist applied    in the next step might function as not only the imaging layer but    also as a passivation layer.)-   Step I: Deposit a resist layer coating 1536A onto passivation layer    1532.-   Step J: Deposit a resist layer coating 1536B onto resist layer    coating 1536A.-   Step K: Laminate a protective, peelable (or water soluble, UV    detachable, etc.) protective polymer sheet 1540 on free surface of    resist layer coating 1536B.-   Step L: Detach stiffener 1504 (FIG. 15K).-   Step M: Deposit resist layer coating 1544A on the free surface of    the aluminum foil temporary substrate 1500.-   Step N: Deposit resist layer coating 1544B onto resist layer coating    1544A.-   Step O: Laminate a protective, peelable (or water soluble, UV    detachable, etc.) protective polymer sheet 1548 on free surface of    resist layer coating 1544B.-   Step P: Expose all resist layer coatings 1536A-B, 1544A-B    simultaneously using dual wavelength maskless lithography/direct    laser writing lithography (see FIG. 7). Note that each of resist    layer coatings 1536B, 1544B differs in composition or spectral    response from corresponding respective underlying resist layer    coatings 1536A, 1544A. Also, each of resist layer coatings 1536B,    1544B is reasonably transparent to the wavelength (be it λ1 or λ1 in    FIG. 7) that will be absorbed by corresponding respective underlying    resist layer coatings 1536A, 1544A. Resist coating layer 1536A may    be identical to resist coating layer 1544A, and resist layer coating    1536B may be equal to resist layer coating 1544B.-   Step Q: Develop resist layer coating 1544B using mask pattern 1552.    Depending upon whether a positive or negative resist is used, the    black portions in top view of mask pattern 1552 illustrated in FIG.    15Q represent either the presence of mask material or the absence of    such material.-   Step R: Etch resist layer coating 1544A and gate metal layer 1508.-   Step S: Etch underlying SiNx insulator layer 1512, hydrogenated    amorphous silicon layer 1516, n+ doped amorphous silicon layer 1520    and S/D metal layer 1524 until the underside of ITO layer 1528 is    reached.-   Step T: Remove any remaining portions resist layer coating 1544B    (FIG. 15S).-   Step U: Develop resist layer coating 1544A, note mask pattern 1556.    Depending upon whether a positive or negative resist is used, the    black portions in top view of mask pattern 1556 illustrated in FIG.    15U represent either the presence of mask material or the absence of    such material.-   Step V: Etch down to SiNx layer 1512 to reveal the gate metal    definition, and also to isolate the gate bus lines from each other.-   Step W: Remove any remaining portions of resist layer coating 1544A    (FIG. 15V).

The following steps are optional.

-   Step X: Deposit a passivation layer 1560.-   Step Y: Deposit pixel capacitors 1564 (opaque or transparent) and    pattern, if required.-   Step Z: Secure a permanent substrate 1568 to passivation layer 1560,    if provided, or to whatever other layer permanent substrate 1568    will be attached to, e.g., using an epoxy 1570. Epoxy 1570 can act    as a passivation layer for gate metal layer 1508 if required.-   Step AA: Develop resist layer coating 1536B (FIG. 15Z). Note    imparted pattern 1572 of this layer.-   Step AB: Etch resist layer coating 1536A as shown using wet etching    or dry etching techniques.-   Step AC: Etch passivation layer 1532, ITO layer 1528, TFT channel    definition/metal layer 1524 (and the isolation sections to isolate    data lines from each other), n+ doped amorphous silicon layer 1520    and partially into hydrogenated amorphous silicon layer 1516.-   Step AD: Remove any remaining portions of resist layer coating 1536B    (FIG. AC).-   Step AE: Develop resist layer coating 1536A (FIG. 15AD). Note    imparted pattern 1576.-   Step AF: Etch passivation layer 1532 to reveal ITO layer 1528    underneath.-   Step AG: Remove any remaining portions of resist layer coating    1536A. Deposit and pattern another passivation layer 1580 on top of    the TFT channel if desired. (This may be done locally only on top of    TFT channel using ink jet, screen printing etc of a suitable organic    or inorganic dielectric layer.)-   Step AH: Deposit/fill an electro-optical material 1584 over pixel    electrode layer 1528.

Regarding Example 13, the following points are noted:

-   1. The recipe of Example 13 allows for a TFT backplane that can be    used in a transmissive LCD and bottom emitting OLED/PLED displays    without any issues with photo induced leakage currents in the TFTs.    Of course, however, this recipe can produce a universally applicable    backplane and may also be used for reflective LCD, front emissive    OLED/PLED, electrophoretics and electrochromic displays, among    others.-   2. Aluminum has a melting point of >650° C. and will easily    withstand the PECVD deposition temperature typically used in    conventional display manufacturing (<450° C.).-   3. In lieu of aluminum foil being used for temporary substrate 1500,    as already described in an earlier section of this disclosure, very    thin nickel or polyimide sheets, among others, may be used.-   4. All patterning of the most critical layers of TFT was effectively    performed at one time. Note that device layers may be deposited in    reverse order (upside down stack) and still yield the same results.    That is, deposit S/D metal layer 1524 first, n+ doped silicon layer    1520 second, hydrogenated amorphous silicon layer 1516 third and    silicon nitride layer 1512 third, and then gate metal layer 1508. Of    course, the mask positions will need to be reversed, as well.-   5. It should be apparent to those skilled in the art that    projection/proximity lithography may readily be substituted for the    contact lithography shown. In addition, maskless amplitude scanning    lithography techniques may also be substituted for the binary masks    illustrated.-   6. This recipe utilizes a two-coating resist layer on each side. The    ITO pixel electrodes can be readily patterned and etched and only    require coarse photolithography registration.-   7. The most critical alignments are between patterns 1552, 1576 for    resist layer coating 1536 (FIGS. 15J and 15Q) and resist layer    coating 1540A (FIGS. 15M and 15AE). The other alignments, i.e., for    resist layer coatings 1536A, 1544B (FIGS. 151, 15N, 15U and 15AA)    are not as critical and may be done at a later time if so desired.-   8. Note that the electro-optical material 1584 for the front plane    (e.g., liquid crystal, OLEDs/PLEDs, electrophoretics,    electrochromic., among others) will be on ITO layer 1528.-   9. This configuration can use the storage-capacitor-on-gate design,    or, alternatively, an independent storage capacitor can be made    using metal or ITO deposition. Such a capacitor (not shown) can be    deposited after the passivation Step X and before lamination to    permanent substrate.-   10. The TFT channel passivation may be readily done using localized    coarse techniques, such as ink jet printing or screen printing using    organic dielectrics, without any further need for patterning.-   11. It will be readily appreciated by those skilled in the art that    using more than resist layer coating per surface provides additional    degrees of freedom in manipulating the TFT pattern.

For example, a black matrix may be integrated into the regionsurrounding the pixel electrode regions. This may be done to increasecontrast or to reduce any photo-induced current in the TFT due to thegate and data line isolation sections that would allow light to impingeon the photoconductive amorphous silicon layers. This black matrix couldbe composed of organic or inorganic materials and may be applied bydeposition or screen printing, among other ways.

-   12. The techniques revealed in this and other examples can be used    to make backplanes for displays, X-rays sensors, RFID tags, image    sensors for applications like optical character recognition, handy    scanners, fingerprint scanners, name card scanners, scanner for    personal computers, facsimile machines, photocopiers, computer aided    design systems, measurement systems and electronic white boards,    among many others.

Example 14

This Example is identical to Example 13 except that there is nodeposition of passivation layer 1532 after Step G (deposition of ITOlayer 1528), i.e., there is no Step H. In such a scheme, only a singleresist layer coating 1536B (FIG. 15J) is required. Correspondingly, onlymask pattern 1552 of FIG. 15Q is needed. In place of passivation layer1532 (FIG. 15H), a passivation layer may be deposited and patternedafter Step AD in the recipe of Example 13 above.

Following are some addition points of note relative to allaforementioned examples and embodiments:

-   1. In lieu of chemical etching, photoablation may be used for    removing the photoresist layers and even the coatings layers, if so    desired.-   2. Photoablation and photo exposure may be integrated so as to    create patterns and define underlying layers together.-   3. The peelable protective coatings applied to the resist layers for    protection may be peeled off prior to resist development.    Alternatively, it may be etched off. Also, the exposure of the    resist layers may be performed through the peelable coatings. In    such cases, it is desirable that the protective coatings be    transparent to the wavelength of light (or stimuli) that will be    used to pattern the resist material.-   4. The recipes of Examples 13 and 14 each utilize more than one    imaging layer (in these examples, coating) per resist layer, as    described. It will be appreciated that if gray scale lithography is    employed, a similar result may be achieved using a single imaging    layer.-   5. It will be clear to skilled artisans that the    channel-width-defining imaging layer (coating) and the    gate-width-defining imaging layer (coating) need to be mutually very    highly aligned. The other imaging layers may be exposed later if    need be. As will be apparent to those skilled in the art, it is    advantageous, though not necessary, to expose all imaging layers at    once.-   6. Inorganic resist materials may be used. Such materials may be    deposited by vacuum evaporation or other techniques to yield layers    having very uniform thickness. This would allow for very high    resolution alignment between the image patterns in the various    imaging layers. Such inorganic resist materials would not require    any baking or other handling required for organic resist materials.    Furthermore, inorganic resist materials may be heated up to high    temperatures without destroying the latent image patterned therein    during exposure. This unique characteristic would allow the    deposition of ITO, pixel capacitor and passivation layers at high    temperature after patterning without concern of resist (imaging)    deterioration.-   7. In current production methodologies for LCD backplanes on glass,    fiduciary marks on the glass surface (coatings and photomasks) serve    as alignment points for the multiple patterning steps that have to    be taken to create a TFT circuit.-   8. It will be readily appreciated by those skilled in the art that    the techniques and methodologies revealed in the present disclosure    may be used not only for opaque (to visible light) semiconductors    materials like amorphous silicon and germanium, but also may be used    to pattern organic semiconductors and transparent conductive oxides    like ZnO, ZnO:Al, TiO₂ and TiO, among others.-   9. As depicted in some of the examples presented, there can be a    concern with photo-induced current in the TFT region due to exposed    amorphous silicon under the gate and data bus lines. This can be    readily address by creating a light-shield structure on top of the    data and gate bus lines using non conductive, dark absorbing black    paint, dye or coating (organic or inorganic). Generally, such    structures are regularly employed in conventional TFT backplane    fabrication technologies and are called “black matrix arrays.” In    the present invention, however black matrix array may be created    both on one surface (data lines) and the other surface (gate lines),    or only on one of these surfaces. In addition, black matrix arrays    may be created on separate substrate (e.g., on a color filter    substrate) or directly on the TFT backplane.-   10. The bonding agent (mechanism) used to bond the permaneny    substrate to the TFT backplane may be an epoxy, adhesive or    silicone, among others, as discussed above. This agent may be    surface modified using plasma or UV radiation, among other things,    to increase bonding strength, if desired. Furthermore, the bonding    agent may be degassed to reduce/eliminate bubble formation during    dispensing and curing. The bonding may take place in a vacuum    environment, controlled gas environment or ambient air, as needed.    Additionally, the bonding agent may serve as a planarization layer    to smooth over and fill in the etched recesses of the TFT circuitry    sheet before lamination. This could be done using liquid monomer,    among other things. The planarization layer curing process may be    activated by heat, light, UV radiation or microwave radiation, among    other things.

As should be apparent from the foregoing disclosure, an EDM method ofthe present invention may be used in making virtually any of a widevariety of displays that compete in the overall display market. Theseinclude, but are not limited to: field-emission displays; LCD displays;OLED displays, including PLED displays; inorganic LED displays;ferroelectric/anti-ferroelectric displays; polymer dispersed liquidcrystal displays; thin and thick film electroluminescent displays; thickdielectric film electroluminescent displays; touch panel displays;electrophoretic displays; electrochromic displays and rotating ball typedisplays. Some of these display are reflective, some are self emissive,whereas others are backlit and/or transparent. As is widely known,active matrix schemes allow for reduced power consumption, higherbrightness and expanded gray scale capabilities.

In addition to the wide applicability of the present invention to thedisplay industry, the present invention is also widely applicable to theelectronics industry more generally. Similar to the production of TFTs,most electrical circuits (resistors, capacitors, inductors, bus lines,electrodes, etc.) can be miniaturized and realized using CMOS, MOS, FET,MOSFET, BJT, JFET and other semiconductor equivalents. Thus, an EDMmethod of the present invention allows for the creation of flexible,conformal, single and multi layer electrical integrated circuits. Thesemay be used to create e.g.: two- and three-dimensional mesa structures;TFTs; thin film diodes; other thin film semiconductor devices, such aselectrodes (eg. ITO and other transparent and opaque electrodes),silicon resistor elements; system on panel; system on chip; driverintegration; integrated signal processors; graphic I/F; small scalememory; ring oscillators; electrodes; switching devices and elements;actuators such as piezoelectric devices; micro mirrors (piezo thin filmceramics); magnetic and magneto-optic recording media and thin filmheads; coils; inductors; thin film material with high permeability;micro magnetic devices which may include semiconductor thin films; superconducting thin films; metallic multi-layered semiconductor thin films;ceramic multi-layered semiconductor thin films and multi-layered thinfilms including organic layers and other layers. All of theaforementioned can be executed in a variety of semiconductor materialtechnologies, whether silicon, CMOS or other technology, including ITT-Vmaterials.

An EDM method of the present invention may also be used to makeintegrated circuit (IC) tags, intelligent IC cards, paper thin smartlabels, ultra-miniaturized electronic products, smart paper, multi chipmodules, implantable chips, identification systems, RFID tags, wearablecomputers, as well as ILED, OLED, PLED and other electroluminescentdevices for use in the lighting industry. These devices may operate notonly in the visible spectrum, but also in the UV, NIR and FIR spectra.

Articles manufactured using an EDM method of the present invention allowfor flexible, less power hungry and portable/mobile instruments. Thereare no particular limitations on the variety of electronic articles thatcan be made. Examples include mobile telephones, mobile video cameras,personal computers, head-mounted displays, and rear- and front-typeprojectors, a digital signal processing apparatuses, personal digitalassistants, electronic organizers, electronic signboards and a displaysfor advertisements/announcements, to name only a few.

As another particular example, an EDM method of the present inventionmay be used un the electronic sensor industry. Most conventional sensorsrely on a sensing element containing built-in circuitry, feed backloops, read out loops, drivers, etc. (or attached circuitry) in order tofunction. Similar sensor “packages” may be readily made using techniquesof the present invention. For example, x-ray imaging sheets are used fora wide variety of applications, such as medical imaging, non-destructivetesting, security imaging in airports and other settings, and home landsecurity, among others. In a particular example, an EDM method of thepresent invention may be used to create large x-ray imaging sheets usedin digital medical platforms. Currently, x-ray imaging sheets aremanufactured in small sizes on rigid platforms. The methodology andtechniques disclosed herein will allow the realization of x-ray sheetson rigid, flexible and/or conformal platforms and on dimensional scalescurrently not feasible. Furthermore, the present invention will allowfor increased resolution sizes for images in medical diagnostics.Methodologies and techniques of the present invention may also be usedto create low-cost, patterned nanotube sensors for toxic gases, medicalmonitoring, industrial controls, etc.

It is known that sensors and actuators can be distributed along thesurfaces of aerospace structures (e.g., wings, fuselage and storagetanks) and can serve to monitor the development of structural flaws,such as cracks, corrosion, voids, de-lamination and joint integrity, orto modify the structure for enhanced performance. However, due toconventional centralized processing of the signals from these sensors,the monitoring system can have hundreds of wire connections and weighhundreds of pounds. Typically, this processing includes amplification,signal conditioning, routing and switching and analog to digitalconversion. The size weight of these systems has limited the use ofthese types of sensing and actuating techniques to specializedflight-test aircraft. There is a great desire to reduce the space andweight of these sensors and actuators, as well as to reduce the localprocessing of the sensor data or control of the actuators in order tomake these systems more widely usable. In addition, the integration ofboth sensors and actuators with TFTs operating at the same high voltagesof the micro electromechanical systems (MEMS) actuators, would benefitthe space and weight requirements.

An EDM method of the present invention may be used to produce TFTs,sensors, and MEMS at low cost with high performance and yield. Such amethod allows for conformal/flexible physical integritymonitoring/actuating devices for continual monitoring and actuating ofaerospace and marine structures for both military and civilian uses. Inaddition, signal processors for analyzing the data may likewise beincorporated in these structures for additional functionality. Thiswould allow for low cost, portable and active methods for thenon-destructive testing and inspection of large multi-shape structures.Additionally, flexible and conformal digital x-ray TFT arrays may alsobe incorporated for such diagnostics.

In another example specific to the field of electronic sensors, tacticalphased-array radar for battlefield applications involve beam-forming andsteering, wherein the shape and angular resolution of a radar beam are afunction of the physical size of the array, the number of radiatingelements and the distance between them. An EDM method of the presentinvention may be used to place active phased array elements on flexiblesubstrates, thereby realizing robust, lightweight, low cost, roll-up,portable (even man portable) antennas of array sizes measured in meters.In contrast, current state-of-the-art antenna manufacturing involvesplacing costly high-performance (i.e., fast switching) transistors,typically in discrete or modular packages, in the right locations withinan array and interconnecting them together. Overall costs for largerarrays rapidly become too high to be economically feasible. The revealedprocess and methodologies allow for roll-to-roll manufacturing of suchphased arrays for military and civilian applications.

An exemplary roll-to-roll (or reel-to-reel) system 1600 of the presentinvention is illustrated in FIG. 16. Roll-to-roll system 1600 may beutilized make virtually any type of circuitry sheet for any of theapplications discussed above. Essentially all that is required for thisis that at least the starting temporary substrate 1604 and the circuitrysheet 1608 as manufactured using roll-to-roll system 1600 be capable ofwinding onto and off of suitable rolls 1612, 1616. Roll-to-roll system1600 may include a suitable number and type of processing stationsnecessary for performing the manufacturing steps necessary. In thepresent example, system 1600 is configured for performing various stepsof EDM method 200 of FIGS. 2A-B. Those skilled in the art will readilyappreciate that system 1600 of FIG. 16 is merely illustrative and thatan actual roll-to-roll system of the present invention for performing amethod of the present invention may indeed include a different number ofstations, different types of stations, different arrangement ofstations, etc., suited for the particular application. It is noted thatsystem 1600 shown is a one-pass system, meaning that the sheet movingthrough the system proceeds in only one direction, generally from unwindroll 1616 to wind roll 1612. Of course, depending upon, e.g., the natureand/or number of the stations utilized, alternative systems of thepresent invention need not be a one-pass system.

Referring now to FIG. 16, and also to FIGS. 2A-B, as mentioned,roll-to-roll system 1600 is generally configured to perform varioussteps of EDM method of FIG. 200, described in detail above. In thisconnection, system 1600 may include a stiffener attaching station 1620at which a stiffener 1624 may be attached to temporary substrate 1604 inthe manner of step A of FIG. 2A. One or more deposition stations 1628may be provided for depositing a device layer stack 1632 to temporarysubstrate 1604 in the manner of step E of FIG. 2A. Although not shown,one or more release layer application stations may be provided forapplying one or more release layers to temporary substrate upstream ofdeposition station(s) 1628 for the purposes discussed above relative tostep D of FIG. 2A.

Downstream of deposition station 1628, roll-to-roll system 1600 mayinclude a resist application station 1636 and a protective layerapplication station 1640 for applying, respectively, a resist layer 1644and a protective layer 1648 over the resist layer in the manner of stepsF and G of FIG. 2A. Next, system 1600 may include a removal station 1652for removing, in this case, stiffener 1624. As discussed above relativeto EDM method 200, removal station 1652 may not be necessary or may bemodified so as to remove part or all of temporary substrate 1604 inaddition to stiffener 1624. System 1600 may also include another resistapplication station 1656 and another protective layer applicationstation 1660 for applying, respectively, a resist layer 1664 and aprotective layer 1668 on the side of device layer stack 1632 oppositeresist and protective layers 1644, 1648 in the manner of steps I and Jof FIG. 2B.

Following protective layer application station 1660, roll-to-roll system1600 may include one or more resist activation stations 1672 one or moreresist developing stations 1676 and one or more material removalstations 1680 arranged in a manner suitable for activating anddeveloping resist layers 1644, 1664, including exposing and developingseparate imaging layers (not shown) within the resist layers, and thenetching the appropriate layers of device layer stack 1632 in the orderrequired for a particular recipe. The activation, e.g., exposure, ofresist layers 1644, 1664 and etching are discussed generally above inconnection with steps K and L, respectively, of FIG. 2B. Resistactivation station 1672 may be a dual-side activation station, as shown,for activating resist layers 1644, 1664 on both sides of device layerstack 1632. For example, resist activation station 1644, 1664 mayinclude, e.g., a multi-wavelength system for exposing multiple imagelevels within one or more resist layers as discussed above in thesection titled “Lithography Techniques”, among others

Downstream of etching station 1680, roll-to-roll system may include apermanent substrate attaching station 1684 for attaching a permanentsubstrate 1688 to the processed resist layer stack 1632 in the manner ofstep M of FIG. 2B. After attaching temporary substrate, circuitry sheet1608 may be wound onto roll 1612. It is noted that for convenience anumber of stations are not shown in FIG. 16, but which those skilled inthe art will readily recognize as being needed for performing variousother steps of the present invention. For example, FIG. 16 does notillustrate roll-to-roll system 1600 has having various passivation layerapplication stations, protective layer removal stations and otherpermanent layer application station(s) for carrying out correspondingrespective steps of a method of the present invention. Those skilled inthe art will readily appreciate if and where any one or more of thesestations should be incorporated into system 1600 given a particularrecipe.

Roll-to-roll system 1600 may further include a suitable controller 1692operatively configured to control the functioning of the system so as toachieve a properly functioning circuitry sheet 1608. Controller 1692 maybe programmed via software and/or hardware to perform the necessarysteps of, e.g., EDM method of FIGS. 2A-B. Depending upon the design ofcontroller 1692, it may be configured for coarse control of roll-to-rollsystem 1600, e.g., control only the positioning of circuitry sheet 1608and the on-off state of the various stations, or it may be configuredfor fine control so as to not only control these aspects, but alsocontrol the functions performed by any one or more or the stations.Those skilled in the art will understand how to design roll-to-rollsystem 1600 and program controller 1692 for any particular application.

Although the invention has been described and illustrated with respectto exemplary embodiments thereof, it should be understood by thoseskilled in the art that the foregoing and various other changes,omissions and additions may be made therein and thereto, without partingfrom the spirit and scope of the present invention.

1. A method of defining at least one defined feature in a substrate,comprising: a) providing a substrate; b) applying a first lowerphotoresist layer on said substrate; c) applying a first upperphotoresist layer on said first lower photoresist layer so as to form afirst photoresist stack; d) exposing said first upper photoresist layerthrough a first mask; e) exposing said first lower photoresist layerthrough a second mask and through said first upper photoresist layersimultaneously with said exposing of said first upper photoresist layerwith said first mask so as to impart a first image of at least one firststructure into said first photoresist stack; f) developing said firstupper photoresist layer and said first lower photoresist layer so thatopenings form in each of said first upper photoresist layer and saidfirst lower photoresist layer to define said at least one firststructure in said first photoresist stack; and g) performing an etch totransfer said at least one first structure formed in said firstphotoresist stack into said substrate so as to form a first definedfeature in said substrate.
 2. A method according to claim 1, whereinstep a) includes providing a substrate having a device coatings stackand step b) includes applying said first lower photoresist layer oversaid device coatings stack.
 3. A method according to claim 1, whereinsaid first mask has a first pattern and step e) includes exposing saidfirst lower photoresist layer through a second mask having a secondpattern differing from said first pattern.
 4. A method according toclaim 1, wherein step b) includes applying a first lower photoresistlayer that is responsive to light of a first wavelength and step c)includes applying a first upper photoresist layer that is responsive tolight of a second wavelength differing from said first wavelength.
 5. Amethod according to claim 4, wherein said first lower photoresist layeris substantially unresponsive to said light of said second wavelength.6. A method according to claim 4, wherein said first upper photoresistlayer is substantially unresponsive to said light of said firstwavelength.
 7. A method according to claim 1, wherein step b) includesapplying a first lower photoresist layer that is responsive to light ofa first wavelength and step c) includes applying a first upperphotoresist layer that is also responsive to said light of said firstwavelength.
 8. A method according to claim 1, wherein said substrate hasa first side and a second side spaced from said first surface, and themethod further comprises: performing steps b) through f) relative tosaid first side of said substrate; applying a second photoresist layeron said second side of said substrate; exposing said second photoresistlayer through at least one mask so as to define in said secondphotoresist layer at least one second structure; developing said secondphotoresist layer so that openings form in said second photoresist layerto define said at least one second structure in said second photoresistlayer; and performing an etch to transfer said at least one secondstructure formed in said second photoresist layer into said substrate soas to form a second defined feature in said substrate.
 9. A methodaccording to claim 8, wherein the step of exposing said secondphotoresist layer through said at least one mask is performedsimultaneously with step d).
 10. A method according to claim 9, furthercomprising performing in a roll-to-roll process steps a) through f) andthe step of exposing said second photoresist layer.
 11. A methodaccording to claim 10, further comprising performing steps a) through f)and the step of exposing said second photoresist layer in forming atleast parts of a plurality of corresponding respective thin filmtransistors.
 12. A method according to claim 9, wherein step a) includesforming a device layer stack on a temporary substrate.
 13. A methodaccording to claim 9, further comprising, prior to each of step b) andthe step of exposing said second photoresist layer, removing saidtemporary substrate.
 14. A method according to claim 8, wherein the stepof applying said second photoresist layer comprises: applying a secondlower photoresist layer on said second side of said substrate; andapplying a second upper photoresist layer on said second lowerphotoresist layer so as to form a second photoresist stack; and the stepof exposing said second photoresist layer through at least one maskcomprises: exposing said second upper photoresist layer through a thirdmask; and exposing said second lower photoresist layer through a fourthmask and through said second upper photoresist layer simultaneously withsaid exposing of said second upper photoresist layer with said thirdmask so as to impart a second image of at least one second structureinto said second photoresist stack.
 15. A method according to claim 14,wherein said first mask has a first pattern, said third mask has a thirdpattern and step e) includes exposing said first lower photoresist layerthrough a second mask having a second pattern differing from said firstpattern and the step of exposing said second lower photoresist layerincludes exposing said second lower photoresist layer through a fourthmask having a fourth pattern differing from said third pattern.
 16. Amethod according to claim 14, wherein steps d) and e) include exposingsaid first upper photoresist layer and said first lower photoresistlayer with corresponding respective differing wavelengths of light. 17.A method according to claim 14, wherein the steps of exposing each ofsaid second upper photoresist layer and said second lower photoresistlayer include exposing said second upper photoresist layer and saidsecond lower photoresist layer with corresponding respective differentwavelengths of light.
 18. A method according to claim 14, wherein thesteps of exposing each of said second upper photoresist layer and saidsecond lower photoresist layer include exposing said second upperphotoresist layer and said second lower photoresist layer with the samewavelength of light.
 19. A method according to claim 14, wherein stepsd) and e) include exposing said first upper photoresist layer and saidfirst lower photoresist layer with the same wavelength of light and thesteps of exposing each of said second upper photoresist layer and saidsecond lower photoresist layer include exposing said second upperphotoresist layer and said second lower photoresist layer with the samewavelength of light.
 20. A method according to claim 14, wherein stepsd) and e) include exposing said first upper photoresist layer and saidfirst lower photoresist layer with differing wavelengths of light andthe steps of exposing each of said second upper photoresist layer andsaid second lower photoresist layer include exposing said second upperphotoresist layer and said second lower photoresist layer with differingwavelengths of light.
 21. A method of defining at least one definedfeature in a substrate, comprising: a) providing a substrate; b)applying a first unitary photoresist layer on said substrate; c)exposing said first unitary photoresist layer through a first mask; d)exposing said first unitary photoresist layer through a second masksimultaneously with said exposing of said first unitary photoresistlayer with said first mask so as to impart an image of at least onefirst structure into said first unitary photoresist layer; e) developingsaid first unitary photoresist layer to define said at least one firststructure; and f) performing an etch to transfer said at least one firststructure formed in said first unitary photoresist layer into saidsubstrate so as to form a first defined feature in said substrate.
 22. Amethod according to claim 21, wherein step a) includes providing asubstrate having a device coatings stack and step b) includes applyingsaid first unitary photoresist layer over said device coatings stack.23. A method according to claim 21, wherein said first mask has a firstpattern and step d) includes exposing said first photoresist layerthrough a second mask having a second pattern differing from said firstpattern.
 24. A method according to claim 21, further includingperforming steps c) and d) using the same wavelength of light.
 25. Amethod according to claim 21, further including performing step c) usinga first wavelength of light and step d) using a second wavelength oflight different from said first wavelength.
 26. A method according toclaim 21, wherein said substrate has a first side and a second sidespaced from said first surface, and the method further comprises:performing steps b) through f) relative to said first side of saidsubstrate; applying a second photoresist layer on said second side ofsaid substrate; exposing said second photoresist layer through at leastone mask so as to define in said second photoresist layer at least onesecond structure; developing said second photoresist layer to definesaid at least one second structure; and performing an etch to transfersaid at least one second structure formed in said second photoresistlayer into said substrate so as to form a second defined feature in saidsubstrate.
 27. A method according to claim 26, wherein the step ofexposing said second photoresist layer through said at least one mask isperformed simultaneously with step d).
 28. A method according to claim27, further comprising performing in a roll-to-roll process steps a)through f) and the step of exposing said second upper photoresist layer.29. A method according to claim 28, further comprising performing stepsa) through f) and the step of exposing said second photoresist layer informing at least parts of a plurality of corresponding respective thinfilm transistors.
 30. A method according to claim 26, wherein step a)includes forming a device layer stack on a temporary substrate.
 31. Amethod according to claim 30, further comprising, prior to step b) andthe step of exposing said second photoresist layer, removing saidtemporary substrate.
 32. A method according to claim 26, wherein thestep of exposing said second photoresist layer through at least one maskcomprises: exposing said second photoresist layer through a third mask;and exposing said second photoresist layer through a fourth masksimultaneously with said exposing of said second photoresist layer withsaid third mask so as to impart an image of at least one secondstructure into said first unitary photoresist layer.
 33. A methodaccording to claim 26, wherein the step of applying said secondphotoresist layer comprises: applying a second lower photoresist layeron said second side of said substrate; and applying a second upperphotoresist layer on said second lower photoresist layer so as to form asecond photoresist stack; and the step of exposing said secondphotoresist layer through at least one mask comprises: exposing saidsecond upper photoresist layer through a third mask; and exposing saidsecond lower photoresist layer through a fourth mask and through saidsecond upper photoresist layer simultaneously with said exposing of saidsecond upper photoresist layer with said third mask so as to impart asecond image of at least one second structure into said secondphotoresist stack.
 34. A method according to claim 33, wherein the stepsof exposing each of said second upper photoresist layer and said secondlower photoresist layer include exposing said second upper photoresistlayer and said second lower photoresist layer with correspondingrespective different wavelengths of light.
 35. A method according toclaim 33, wherein the steps of exposing each of said second upperphotoresist layer and said second lower photoresist layer includeexposing said second upper photoresist layer and said second lowerphotoresist layer with the same wavelength of light.
 36. A methodaccording to claim 33, wherein the step of exposing said secondphotoresist layer is performed simultaneously with step d).
 37. A methodaccording to claim 33, wherein step d) and the step of exposing saidsecond photoresist layer together include exposing said first unitaryphotoresist layer and said second photoresist layer with correspondingrespective differing wavelengths of light.
 38. A method according toclaim 33, wherein each of step d) and the step of exposing said secondphotoresist layer includes exposing said first unitary photoresist layerand said second photoresist layer with the same wavelength of light.